ARM: mvebu: defconfig: update ...

Enable remaining boards and enable some more features.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: add basic support for the Armada XP DB platform ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi3: remove swapped sdhci and sdhost ...

Now that we have a sdhost driver there is no need to swap those
peripherals. As the sdhci peripheral is only used for SDIO, which
isn't supported in Barebox disable it.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi: enable sdhost driver in defconfig ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi: add clock for sdhost ...

The sdhost is driven by the core clock.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: aarch64: do not use 32bit optimized find bit functions ...

The optimized find bit functions are only implemented for 32 bit and are
not built on aarch64 systems. Therefore, for example bootchooser cannot
be build for aarch64.

Select the generic find_bit implementations on aarch64.

As the decision, if lib64 or lib32 is build or not, directly depends on
CPU_V8, the generic implementation also should be used if CPU_V8 is
selected.

Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zii-imx8mq-dev: select ZII_COMMON ...

The RDU3 shares some of the board fixups with the other Zii boards.
For those to work ZII_COMMON needs to be enabled.

Fixes: d76ba38a1605 (ARM: zii-common: reuse i210 config check for RDU3)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx: disable IPU QoS setup for correct SoCs ...

The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't
execute IPU QoS setup on MX6 SX/SL"), but instead it bails at
the Solo, not the SX and SL.

The original intent was most probably to add an exception for
the i.MX6 Solo as well, so everything else is skipped, including
the SX, SL and now the UL and ULL. Fix the code to reflect this.

On the SX, SL, UL, ULL, this now avoids writes to memory, which
isn't described in the datasheets. On the S, it now configures
the QoS settings.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: mark uncached regions as eXecute never on v7 ...

The ARM Cortex-A Series Programmer's Guide notes[1]:
> When set, the Execute Never (XN) bit in the translation table entry
> prevents speculative instruction fetches taking place from desired
> memory locations and will cause a prefetch abort to occur if execution
> from the memory location is attempted.
>
> Typically device memory regions are marked as execute never to prevent
> accidental execution from such locations, and to prevent undesirable
> side-effects which might be caused by speculative instruction fetches.

Heed the advice and mark uncached memory with the XN bit, when the
CPU is >=v7.

It's possible that there are SoCs that have a section shared between
device memory and the on-chip RAM hosting the PBL.
In such a section, every page except for the OCRAM's should be mapped XN,
but as we know of no SoC with such an OCRAM layout, we ignore this
possibility for now and let mmu_early_enable map sections only.

[1]: 9.6.3 "Execute Never", Version 4.0

Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: remove doubly defined macro ...

PMD_SECT_DEF_CACHED is defined along with PMD_SECT_DEF_UNCACHED
in mmu.h, which is included two lines prior.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: start invalidation from outer levels ...

On 25/4/19 11:57, Lucas Stach wrote:
> [T]he sequence that could go wrong in Barebox is as follows:
> 1. CPU core starts invalidating at L1 cache level
> 2. HW prefetcher decides that a specific address should be brought into
> the L1 cache.
> 3. HW prefetcher finds a valid block for the requested address in L2
> cache and moves cached data from L2 to L1.
> 4. Only now CPU core invalidates L2 cache.
>
> In the above sequence we now have invalid data in the L1 cache line.
> The correct sequence will avoid this issue:
>
> 1. CPU core starts invalidating at L2 cache level
> 2. HW prefetcher decides that a specific address should be brought into
> the L1 cache.
> 3. HW prefetcher sees invalid tags for the requested address in L2
> cache and brings in the data from external memory.
> 4. CPU core invalidates L1 cache, discarding the prefetched data.
>

The ARM Cortex-A Series Programmer's Guide addresses this issue
in the SMP-context[1]:
> If another core were to access the affected address between those
> two actions, a coherency problem can occur. Such problems can be avoided
> by following two simple rules.
>
> * When cleaning, always clean the innermost (L1) cache first and then
>   clean the outer cache(s).
> * When invalidating, always invalidate the outermost cache first and
>   the L1 cache last.

The current code correctly iterates from inner to outer cache levels
when flushing/cleaning (r8 == 0), invalidation (r8 == 1) occurs in the
same direction though. Adjust the invalidation iteration order to start
from the outermost cache instead.

Equivalent C-Code:

	enum cache_op { CACHE_FLUSH = 0, CACHE_INVAL = 1 };
	register enum cache_op operation asm("r8");
	register int i asm("r12");
	register int limit asm("r3") = max_cache_level << 1; // e.g. 4 with L2 max

	+if (operation == CACHE_FLUSH) {
	 	i = 0;
	+} else {
	+	i = limit - 2;
	+}

	 bool loop_again;
	 do {
		/* [snip] */
	+	if (operation == CACHE_FLUSH) {
			i += 2;
			loop_again = limit > i;
	+	} else {
	+		loop_again = i > 0;
	+		i -= 2;
	+	}
	} while (loop_again);

[1]: 18.6 "TLB and cache maintenance broadcast", Version 4.0

Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: work around Cortex-A7 erratum 814220 ...

This patch is based on 0e9a87bb from the linux-imx kernel:
------------------------------------------------------------------------------
| ARM/MP: 814220—B-Cache maintenance by set/way operations can execute
| 	out of order.
|
| Description:
| The v7 ARM states that all cache and branch predictor maintenance operations
| that do not specify an address execute, relative to each other, in program
| order. However, because of this erratum, an L2 set/way cache maintenance
| operation can overtake an L1 set/way cache maintenance operation, this would
| cause the data corruption.
|
| This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
|
| This patch is the SW workaround by adding a DSB before changing cache levels
| as the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.
| Signed-off-by: Jason Liu <r64343@freescale.com>
------------------------------------------------------------------------------

It was later posted to LKML for Linux inclusion, but is not yet mainline:
<20190214083145.15148-1-benjamin.gaignard@linaro.org>

Unlike the Linux version, we don't make the barrier dependent on a
Kconfig option and always execute the dsb:

On 25/4/19 12:02, Lucas Stach wrote:
> I don't think we need a Kconfig option here. This function is not
> really performance critical. The short pipeline stall introduced by the
> dsb when switching the cache level is minor compared to the time it
> takes to actually move the cache blocks on a clean.
>
> Just always execute the [dsb] and add a comment on why it is needed.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zii-vf610-dev: Add ZII SSMB DTU board ...

Add the Zodiac Digital Tapping Unit, a VF610 based network device with
5 Ethernet ports.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init() ...

There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3,
SCTLR will be in a state we expect it to be. Add code to reset it to a
known state, so we'd always start form clean slate. This is also
matches what we've been doing non 64-bit ARMs.

Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon
appear to have different mask ROM behaviour where it now leaves MMU
enabled if no valid boot source is found. Page table it sets up
doesn't include DDR range, so trying to bootstrap the device via
JTAG/OpenOCD results in an abort.

The value for SCTLR_ELx_FLAGS was taken from Linux kernel.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Shell: Handle aborting loops better ...

It's easy to get stuck in an infinite loop in the hush shell:

while true; do sleep 1; done

The 'sleep' command will check for ctrl-c with the ctrlc() function. This
will abort the sleep command. Hush then checks for ctrl-c again in the
loop. The ctrl-c in the buffer has already been eaten by the sleep
command, so the loop will continue.

With this patch we remember the presence of a ctrl-c character in a
variable instead of checking for a new character each time. The
variable must be resetted explicitly by calling ctrlc_handled() which
will be called by the shell in the outer loop.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zii-imx8mq-dev: Drop unnecessary barrier() in switch statement ...

AArch64 uses PC-relative addressing instead of absolute one for data
lookups, so compiling switch statement into a LUT shouldn't be a
problem regardless if relocation happened or not. Disassembly of PBL
code looks almost exactly the same with or without this workaround, so
it is clearly not needed. Drop it.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Chris Healy <cphealy@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zii-imx51-rdu1: Use -fno-tree-switch-conversion -fno-jump-tables ...

Original and very poor workaround no longer works against GCC8, so
drop it and replace with a proper solution that should've been used in
the first place - specifying -fno-tree-switch-conversion
-fno-jump-tables as CFLAGS when building lowlevel.c

Tested to work with:

    - GCC 8.2.1 (arm-none-eabi)
    - GCC 7.1.0 (arm-none-eabi)
    - GCC 4.8.4 (armv7l-timesys-linux-gnueabihf)

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Chris Healy <cphealy@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zii-vf610-dev: Use -fno-tree-switch-conversion -fno-jump-tables ...

Original and very poor workaround no longer works against GCC8, so
drop it and replace with a proper solution that should've been used in
the first place - specifying -fno-tree-switch-conversion
-fno-jump-tables as CFLAGS when building lowlevel.c

Tested to work with:

    - GCC 8.2.1 (arm-none-eabi)
    - GCC 7.1.0 (arm-none-eabi)
    - GCC 4.8.4 (armv7l-timesys-linux-gnueabihf)

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Chris Healy <cphealy@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx8mq: link PCIE1 and PCIE2 power domains ...

Those two power domains can only be used together. The link between
the two has been dropped with the dts merge of v5.1-rc1. Fix this.

Fortunately the i.MX8MQ PCIe support will land in Linux 5.2, so we
can drop all those PCIe related local DT overrides with the next big
dts upstream sync.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: Cyclone5: remove watchdog_disable() ...

watchdog_disable() is left over from the original SoCFPGA commit and
nothing calls it.  Remove it to avoid a '-Wmissing-prototypes' warning
from the compiler.

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: remove request_sdram_region "fdt" ...

It is actually not needed at barebox runtime

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: relocation: do not use configurable memory layout ...

The relocator is not able to patch properly new location of
the stack. To make it work properly it is better to disable
HAVE_CONFIGURABLE_MEMORY_LAYOUT.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: relocation: add relocation support ...

this patch i a port of following patch from u-boot with some additional
integration changes and fixes of original code:
| Subject: [PATCH] MIPS: Stop building position independent code
|
| U-Boot has up until now built with -fpic for the MIPS architecture,
| producing position independent code which uses indirection through a
| global offset table, making relocation fairly straightforward as it
| simply involves patching up GOT entries.
|
| Using -fpic does however have some downsides. The biggest of these is
| that generated code is bloated in various ways. For example, function
| calls are indirected through the GOT & the t9 register:
|
|   8f998064   lw     t9,-32668(gp)
|   0320f809   jalr   t9
|
| Without -fpic the call is simply:
|
|   0f803f01   jal    be00fc04 <puts>
|
| This is more compact & faster (due to the lack of the load & the
| dependency the jump has on its result). It is also easier to read &
| debug because the disassembly shows what function is being called,
| rather than just an offset from gp which would then have to be looked up
| in the ELF to discover the target function.
|
| Another disadvantage of -fpic is that each function begins with a
| sequence to calculate the value of the gp register, for example:
|
|   3c1c0004   lui    gp,0x4
|   279c3384   addiu  gp,gp,13188
|   0399e021   addu   gp,gp,t9
|
| Without using -fpic this sequence no longer appears at the start of each
| function, reducing code size considerably.
|
| This patch switches U-Boot from building with -fpic to building with
| -fno-pic, in order to gain the benefits described above. The cost of
| this is an extra step during the build process to extract relocation
| data from the ELF & write it into a new .rel section in a compact
| format, plus the added complexity of dealing with multiple types of
| relocation rather than the single type that applied to the GOT. The
| benefit is smaller, cleaner, more debuggable code. The relocate_code()
| function is reimplemented in C to handle the new relocation scheme,
| which also makes it easier to read & debug.
|
| Taking maltael_defconfig as an example the size of u-boot.bin built
| using the Codescape MIPS 2016.05-06 toolchain (gcc 4.9.2, binutils
| 2.24.90) shrinks from 254KiB to 224KiB.
|
| Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: relocation: pass ram size to pbl_main_entry ...

To make barebox dynamically relocatable it should know
the RAM size to be able to calculate proper new location.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX25: Add some more clocks ...

Add some clocks needed for:
- RNGB
- SCC
- Dryice RTC

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/zynqmp'

Merge branch 'for-next/warnings'

Merge branch 'for-next/stm32'

Merge branch 'for-next/misc'

Merge branch 'for-next/lseek'