spi: Kconfig: remove dependency list from Freescale QSPI controller ...

The dependency list for the Freescale QSPI controller doesn't match
the SoCs the hardware is in at all. Remove the dependency entirely as
the driver builds on all machines.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/qspi'

Merge branch 'for-next/mmc'

Merge branch 'for-next/misc'

Merge branch 'for-next/layerscape'

Merge branch 'for-next/imx'

esdhc-xload: invalidate icache before jumping to image ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: fsl-fman: Sync rx buffers for device initially ...

The rx buffers must be given to the device initially to work properly.
Otherwise the first packets are corrupted.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: Add support for more Macronix devices ...

Add support for the Macronix mx66u51235f, mx66l1g45g and mx66l1g55g.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ddr: fsl: move fsl_ddr_set_memctl_regs prototype to include/ ...

fsl_ddr_set_memctl_regs() is not only used internally in the DDR
controller driver, but can also be called by the boards to configure
a static setting. Move the prototype to include/ where it can be
used by board code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: ls1046a: Set better divider values ...

MMC Frequency was set to something like 55MHz. This doesn't work for all
SD cards. Set to 25MHz which is supported by all SD cards.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: devices: m25p80: use the spi_mem_xx() API ...

This is the barebox adoption of the linux v4.16 patch

  4120f8d
  Author:     Boris Brezillon <bbrezillon@kernel.org>
  AuthorDate: Thu Apr 26 18:18:19 2018 +0200
  Commit:     Mark Brown <broonie@kernel.org>
  CommitDate: Fri May 11 11:33:51 2018 +0900

  mtd: spi-nor: Use the spi_mem_xx() API

  The spi_mem_xxx() API has been introduced to replace the
  spi_flash_read() one. Make use of it so we can get rid of
  spi_flash_read().

  Note that using spi_mem_xx() also simplifies the code because this API
  takes care of using the regular spi_sync() interface when the optimized
  ->mem_ops interface is not implemented by the controller.

  Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
  Reviewed-by: Frieder Schrempf <frieder.schrempf@exceet.de>
  Tested-by: Frieder Schrempf <frieder.schrempf@exceet.de>
  Signed-off-by: Mark Brown <broonie@kernel.org>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: provide default erase_sector implementation ...

Based on the Linux v4.4 patch

commit c67cbb8
Author:     Brian Norris <computersforpeace@gmail.com>
AuthorDate: Tue Nov 10 12:15:27 2015 -0800
Commit:     Brian Norris <computersforpeace@gmail.com>
CommitDate: Thu Nov 19 13:34:44 2015 -0800

    mtd: spi-nor: provide default erase_sector implementation

    Some spi-nor drivers perform sector erase by duplicating their
    write_reg() command. Let's not require that the driver fill this out,
    and provide a default instead.

    Tested on m25p80.c and Medatek's MT8173 SPI NOR flash driver.

    Signed-off-by: Brian Norris <computersforpeace@gmail.com>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: introduce SPI 1-2-2 and SPI 1-4-4 protocols ...

Sync the driver with Linux v4.12 and apply the patch

  commit cfc5604
  Author:     Cyrille Pitchen <cyrille.pitchen@atmel.com>
  AuthorDate: Tue Apr 25 22:08:46 2017 +0200
  Commit:     Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
  CommitDate: Mon May 15 21:56:17 2017 +0200

      mtd: spi-nor: introduce SPI 1-2-2 and SPI 1-4-4 protocols

      This patch changes the prototype of spi_nor_scan(): its 3rd parameter
      is replaced by a 'struct spi_nor_hwcaps' pointer, which tells the spi-nor
      framework about the actual hardware capabilities supported by the SPI
      controller and its driver.

      Besides, this patch also introduces a new 'struct spi_nor_flash_parameter'
      telling the spi-nor framework about the hardware capabilities supported by
      the SPI flash memory and the associated settings required to use those
      hardware caps.

      Then, to improve the readability of spi_nor_scan(), the discovery of the
      memory settings and the memory initialization are now split into two
      dedicated functions.

      1 - spi_nor_init_params()

      The spi_nor_init_params() function is responsible for initializing the
      'struct spi_nor_flash_parameter'. Currently this structure is filled with
      legacy values but further patches will allow to override some parameter
      values dynamically, for instance by reading the JESD216 Serial Flash
      Discoverable Parameter (SFDP) tables from the SPI memory.
      The spi_nor_init_params() function only deals with the hardware
      capabilities of the SPI flash memory: especially it doesn't care about
      the hardware capabilities supported by the SPI controller.

      2 - spi_nor_setup()

      The second function is called once the 'struct spi_nor_flash_parameter'
      has been initialized by spi_nor_init_params().
      With both 'struct spi_nor_flash_parameter' and 'struct spi_nor_hwcaps',
      the new argument of spi_nor_scan(), spi_nor_setup() computes the best
      match between hardware caps supported by both the (Q)SPI memory and
      controller hence selecting the relevant settings for (Fast) Read and Page
      Program operations.

      Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
      Reviewed-by: Marek Vasut <marek.vasut@gmail.com>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

spi: add driver for Freescale QSPI controller ...

This is based on the Linux v5.1-rc1 driver introduced with the commit:

  commit 84d0431
  Refs: v5.0-rc1-1-g84d043185dbe
  Author:     Frieder Schrempf <frieder.schrempf@kontron.de>
  AuthorDate: Mon Jan 7 09:29:47 2019 +0000
  Commit:     Mark Brown <broonie@kernel.org>
  CommitDate: Mon Jan 7 16:56:24 2019 +0000

      spi: Add a driver for the Freescale/NXP QuadSPI controller

      This driver is derived from the SPI NOR driver at
      mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
      of the SPI framework to issue flash memory operations to up to
      four connected flash chips (2 buses with 2 CS each).

      The controller does not support generic SPI messages.

      This patch also disables the build of the "old" driver and reuses
      its Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it.

      Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
      Acked-by: Han Xu <han.xu@nxp.com>
      Reviewed-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
      Tested-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
      Tested-by: Han Xu <han.xu@nxp.com>
      Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
      Signed-off-by: Mark Brown <broonie@kernel.org>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: remove unused write_enable from write_reg ...

Based on the Linux v4.2 commit:

  commit f9f3ce8
  Author:     Jagan Teki <jteki@openedev.com>
  AuthorDate: Wed Aug 19 15:26:44 2015 +0530
  Commit:     Brian Norris <computersforpeace@gmail.com>
  CommitDate: Fri Sep 11 16:04:55 2015 -0700

      mtd: spi-nor: Zap unneeded write_enable from write_reg

      The 'write_enable' argument is unused and unneeded, so remove it from
      the API.

      Signed-off-by: Jagan Teki <jteki@openedev.com>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Han Xu <han.xu@freescale.com>
      [Brian: fixed for nxp-spifi.c]
      Signed-off-by: Brian Norris <computersforpeace@gmail.com>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

spi: Extend the core to ease integration of SPI memory controllers ...

Sync with Linux v5.1-rc1.

This is the barebox adoption of the commit

  commit c36ff26
  Author: Boris Brezillon <boris.brezillon@bootlin.com>
  Date:   Thu Apr 26 18:18:14 2018 +0200

      spi: Extend the core to ease integration of SPI memory controllers

      Some controllers are exposing high-level interfaces to access various
      kind of SPI memories. Unfortunately they do not fit in the current
      spi_controller model and usually have drivers placed in
      drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI
      memories in general.

      This is an attempt at defining a SPI memory interface which works for
      all kinds of SPI memories (NORs, NANDs, SRAMs).

      Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
      Reviewed-by: Frieder Schrempf <frieder.schrempf@exceet.de>
      Tested-by: Frieder Schrempf <frieder.schrempf@exceet.de>
      Signed-off-by: Mark Brown <broonie@kernel.org>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

spi: Generalize SPI "master" to "controller" ...

Sync with Linux v5.1-rc1.

This is the barebox adoption of the commit

  commit 8caab75
  Author: Geert Uytterhoeven <geert+renesas@glider.be>
  Date:   Tue Jun 13 13:23:52 2017 +0200

      spi: Generalize SPI "master" to "controller"

      Now struct spi_master is used for both SPI master and slave controllers,
      it makes sense to rename it to struct spi_controller, and replace
      "master" by "controller" where appropriate.

      For now this conversion is done for SPI core infrastructure only.
      Wrappers are provided for backwards compatibility, until all SPI drivers
      have been converted.

      Noteworthy details:
	- SPI_MASTER_GPIO_SS is retained, as it only makes sense for SPI
	  master controllers,
	- spi_busnum_to_master() is retained, as it looks up masters only,
	- A new field spi_device.controller is added, but spi_device.master is
	  retained for compatibility (both are always initialized by
	  spi_alloc_device()),
	- spi_flash_read() is used by SPI masters only.

      Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
      Signed-off-by: Mark Brown <broonie@kernel.org>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: cadence: add cqspi_set_protocol ...

Sync up the driver with the original linux v4.7 driver version.

As only Quad-SPI mode is/was supported, the function was not
ported in the initial move to barebox.
To make future synchronizations with the kernel driver easier,
add this function and reorder the functions in the driver
accordingly.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: add driver for BCM283x sdhost core ...

The sdhost is a simple MMC controller found on the Broadcom
BCM283x line of SoCs. The driver code was ported from U-Boot
and then simplified a bit, by dropping a lot of the state
tracking.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

UBI: remove Kconfig entry from include ...

CONFIG_MTD_UBI_WL_THRESHOLD can be set via Kconfig.
default there is also 4096. So remove the leftover here.

Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: vf610: improve handling case that cpu frequency can't be changed ...

Currently we get a nasty error message if the cpu clock can't be
changed:
DDRC is clocked by PLL1, can't switch CPU clockinitcall vf610_switch_cpu_clock+0x1/0x198 failed: Invalid argument

So let's do the following:
- factor out the check from vf610_switch_cpu_clock_to_500mhz() and
  vf610_switch_cpu_clock_to_400mhz
- if clock can't be changed, don't treat it as an error
- don't call clock notifier chain if clock can't be changed
- add trailing newline to the warning message

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: add Winbond W25Q40BW ...

This 4MBit SPI chip can be found in Kindle Voyage devices

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add i.MX25 rtc driver ...

This adds a RTC driver for the Freescale i.MX25. This is done more
to get access to the nonvolatile general purpose register than it
is done to read the clock.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX25: Add some more clocks ...

Add some clocks needed for:
- RNGB
- SCC
- Dryice RTC

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

crypto: caam: add blobgen driver ...

The blobgen driver allows generating and reading of red blobs on the
i.MX6 CAAM crypto core.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

crypto: add new imx-scc driver ...

The Security Controller (SCC) is found on (at least) i.MX25 SoCs.
It is not a crypto engine in the usual sense. The only supported
algorithm in hardware is 3DES and the key is not configurable, but
is fused in the hardware.

The SCC can be handed some block of data in the red memory space
and it will return the encrypted data in the black memory space and
vice versa.

The API for this driver are the functions

  - mxc_scc_cbc_des_encrypt
  - mxc_scc_cbc_des_decrypt

Along with this driver a blobgen implementation is provided.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

crypto/caam: Add missing include ...

rng_self_test.c doesn't include the header file providing the
prototypes for the functions it implements. Add the missing include.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

hab/caam: Fix compilation of caam driver when hab is disabled ...

The caam driver needs the variable habv4_need_rng_software_self_test,
but this is only declared when HABV4 is enabled. Instead of exporting
a variable rather provide a function to test if a software selftest
of the random number generator is needed.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: socfpga: fix compiler warnings for Cyclone5 ...

When building for Cyclone5 SoCFPGA, the socfpga_a10_pll_init(),
socfpga_a10_perith_init() and socfpga_a10_gate_init() functions are
defined as dummy functions returning ERR_PTR(-ENOSYS).  They are defined
with external linkage.  With '-Wmissing-prototypes' GCC warns about
externally linked function definitions with no preceding prototype.
Define them as 'static inline' to avoid the compiler warnings.

(Note: Arria10 uses non-dummy versions of these functions declared
'extern' but defined elsewhere.)

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>