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LuminaSensum / barebox

History for barebox / arch

2019-12-09	86d711f Browse files » Merge branch 'for-next/zynq' Sascha Hauer committed on 9 Dec 2019
	4b05f14 Browse files » Merge branch 'for-next/usb' Sascha Hauer committed on 9 Dec 2019
	06f66d8 Browse files » Merge branch 'for-next/stm32' Sascha Hauer committed on 9 Dec 2019
	77d783a Browse files » Merge branch 'for-next/randfixes' Sascha Hauer committed on 9 Dec 2019
	293e981 Browse files » Merge branch 'for-next/pci' Sascha Hauer committed on 9 Dec 2019
	056196b Browse files » Merge branch 'for-next/misc' Sascha Hauer committed on 9 Dec 2019
	e0b4ef8 Browse files » Merge branch 'for-next/layerscape' Sascha Hauer committed on 9 Dec 2019
	1a94fdf Browse files » Merge branch 'for-next/imx' Sascha Hauer committed on 9 Dec 2019
	f8614d9 Browse files » Merge branch 'for-next/gpio' Sascha Hauer committed on 9 Dec 2019
	eaaa4c8 Browse files » x86: efi: lds: don't discard any relocation sections ... The incoming EFI PCI root bridge IO protocol driver will register PCI fixups. Executing them will fail because the hook function's relocation information is stripped from the final barebox.efi binary. Instead of adding each section by name, just keep all .rela* sections in the final binary. This doesn't yet increase the size of the resulting barebox (yet). Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Ahmad Fatoum authored on 4 Dec 2019 Sascha Hauer committed on 9 Dec 2019
2019-12-06	e9e329f Browse files » ARM: boards: phytec-som-imx6: Replace spi by spi-nor in bootsource script ... Commit 7802c6f891b7 ("ARM: i.MX6: boot: Return BOOTSOURCE_SPI_NOR, not BOOTSOURCE_SPI") changed the returned boot source for SPI NOR on i.MX 6 from SPI to SPI_NOR. This needs to be accounted for in the bootsource scripts. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Stefan Riedmueller authored on 3 Dec 2019 Sascha Hauer committed on 6 Dec 2019
2019-12-04	fd2c41f Browse files » ARM: VFxxx: Display UID information on boot ... Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 2 Dec 2019 Sascha Hauer committed on 4 Dec 2019
2019-12-02	f172219 Browse files » ARM: mvebu: correct DTB rule for MARVELL_ARMADA_XP_DB ... Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	2352c0b Browse files » ARM: omap: pfc200: NAND support requires CONFIG_OMAP_GPMC ... Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	2d67763 Browse files » ARM: davinci: virt2real: select OFTREE and OFDEVICE ... The board probes from DT, so there is no point in allowing a configuration without OF support. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	00e86ec Browse files » ARM: layerscape: ppa: use sync_for_execution instead of a manual cache flush ... The copied code is then jumped to, so we need to sync the caches for execution instead of just flushing the data caches. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	a17d92b Browse files » pinctrl: at91pio4: move to correct location in Kconfig ... The driver also depends on PINCTRL, so we should only allow it to be enabled if this option is selected. We can also drop the OFDEVICE dependency then, as this is required for PINCTRL. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	89951c8 Browse files » ARM: layerscape: select OFTREE and OFDEVICE ... The Layerscape architectures probes exclusively from DT, so make sure the correct config options are enabled. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	1d14e26 Browse files » ARM: ARM_SMCCC is only available on >= ARMv7 ... So anything selecting this option must depend on those CPU architectures. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	07b468c Browse files » ARM: layerscape: add missing selects for TQMLS1046A ... Make sure that all the lowlevel components are selected when only this board is built. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	1379826 Browse files » ARM: mxs: bcb: declare locally used functions as static ... Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	b52afc9 Browse files » ARM: psci: declare locally used functions as static ... Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	4af1553 Browse files » ARM: implement CONFIG_PBL_BREAK for ARM64 ... ARM64 uses a different assembler mnemonic for the breakpoint. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
	39ae48a Browse files » ARM: move into ARM32 specific optee kernel start into lib32 dir ... Otherwise it may also get built on a ARM64 config, which obviously fails. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Nov 2019 Sascha Hauer committed on 2 Dec 2019
2019-11-28	3885852 Browse files » ARM: Layerscape: PPA: Disable CAAM JR used by secure firmware ... JR3 is used by the secure firmware. We have to remove the node from the Linux device tree to prevent Linux from using it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 28 Nov 2019
	904d2c2 Browse files » ARM: Layerscape: TQMLS1046a: Fix partition name ... The barebox partition on the SD card starts at offset 0x1000, so the partition node should be named partition@1000. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 28 Nov 2019
	03d8054 Browse files » ARM Layerscape: ls1046ardb: read nxid eeprom ... This adds support for reading the EEPROM which has a "NXID" data structure on it. The MAC addresses for the ethernet devices are found here which are registered with this patch. The NXID data structure is also found on other NXP Layerscape boards, so once we support other boards the code should be moved somewhere where it can be shared between boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 28 Nov 2019
2019-11-27	fa2081d Browse files » MIPS: Makefile: minor codingstyle fix ... it exceeds 80 chararacters per line, but is more readable and agrees agrees with the previous lines. Signed-off-by: Du Huanpeng <duhuanpeng@loongson.cn> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Du Huanpeng authored on 26 Nov 2019 Sascha Hauer committed on 27 Nov 2019
	afdb720 Browse files » ARM64: Switch to 4 level page tables ... 3 level page tables only allow to resolve 39 bit addresses. Switch to 4 level page tables to add support for bigger physical address ranges. This is needed for example on Layerscape SoCs where the PCI windows are outside the 39bit range. The early MMU support still uses 39bit addressing. We only use a single level page table in early MMU support and with 48bit addresses we wouldn't have enough granularity to map the SDRAM differently then the rest of the address space. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 27 Nov 2019
	08bad2f Browse files » ARM Layerscape: ls1046ardb: Fix EEPROM nodes ... The ls1046ardb only has one EEPROM instead of two and this is a 24c04 (which spans two addresses on the I2C bus) and not a 24c512. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 27 Nov 2019