/*******************************************************************************
* \file cy8c6xx7_cm4_dual.icf
* \version 2.90.1
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;

/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
 * More about CM0+ prebuilt images, see here:
 * https://github.com/cypresssemiconductorco/psoc6cm0p
 */
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE  = 0x2000;

if (!isdefinedsymbol(MBED_ROM_START)) {
  define symbol MBED_ROM_START = 0x10000000;
}

/* MBED_APP_START is being used by the bootloader build script and
 * will be calculate by the system. In case if MBED_APP_START address is
 * customized by the bootloader config, the application image should not
 * include CM0p prebuilt image.
 */
if (!isdefinedsymbol(MBED_APP_START)) {
  define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE);
}

if (!isdefinedsymbol(MBED_ROM_SIZE)) {
  define symbol MBED_ROM_SIZE = 0x00100000;
}

/* MBED_APP_SIZE is being  used by the bootloader build script and
 * will be calculate by the system.
 */
if (!isdefinedsymbol(MBED_APP_SIZE)) {
  define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE);
}

if (!isdefinedsymbol(MBED_RAM_START)) {
  define symbol MBED_RAM_START = 0x08002000;
}

if (!isdefinedsymbol(MBED_RAM_SIZE)) {
  define symbol MBED_RAM_SIZE = 0x00045800;
}

if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {

    if (!isdefinedsymbol(__STACK_SIZE)) {
      define symbol MBED_BOOT_STACK_SIZE = 0x0400;
    } else {
      define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
    }
}

define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;

/* The symbols below define the location and size of blocks of memory in the target.
 * Use these symbols to specify the memory regions available for allocation.
 */

/* The following symbols control RAM and flash memory allocation for the CM4 core.
 * You can change the memory allocation by editing RAM and Flash symbols.
 * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
 * Using this memory region for other purposes will lead to unexpected behavior.
 * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
 * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
 */
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__   = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__   = (MBED_ROM_START + FLASH_CM0P_SIZE - 1);

define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__   = (MBED_APP_START + MBED_APP_SIZE - 1);

/* The following symbols define a 32K flash region used for EEPROM emulation.
 * This region can also be used as the general purpose flash.
 * You can assign sections to this memory region for only one of the cores.
 * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
 * Therefore, repurposing this memory region will prevent such middleware from operation.
 */
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;

/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;

/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;

/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;

/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;

/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;

/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;

/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;

define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__   = 0x0;


define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
/*-Sizes-*/
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
    define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/

define memory mem with size = 4G;
define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__];
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];

define block RAM_DATA {readwrite section .data};
define block RAM_OTHER {readwrite section * };
define block RAM_NOINIT {readwrite section .noinit};
define block RAM_BSS {readwrite section .bss};
define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};

define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };

define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
define block RO     {first section .intvec, readonly};

define block cy_xip { section .cy_xip };

/*-Initializations-*/
initialize by copy { readwrite };
do not initialize  { section .noinit, section .intvec_ram };

/*-Placement-*/

/* Flash - Cortex-M0+ application image */
place at start of IROM0_region  { block CM0P_RO };

/* Flash - Cortex-M4 application */
place at start of IROM1_region  { block RO };

/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };

/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };

/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };

/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };

/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };

/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };

/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };

/* eFuse */
".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };

/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region  { block cy_xip };

/* RAM */
place at start of IRAM1_region  { readwrite section .intvec_ram};
place in IRAM1_region  { block RAM};
place in IRAM1_region  { block HEAP};
place at end   of IRAM1_region  { block CSTACK };

/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };


keep {  section .cy_m0p_image,
        section .cy_app_signature,
        section .cy_em_eeprom,
        section .cy_sflash_user_data,
        section .cy_sflash_nar,
        section .cy_sflash_public_key,
        section .cy_toc_part2,
        section .cy_rtoc_part2,
        section .cy_efuse,
        section .cy_xip,
        section .cymeta,
         };


/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start    = 0x10000000;
define exported symbol __cy_memory_0_length   = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;

/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start    = 0x14000000;
define exported symbol __cy_memory_1_length   = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;

/* Supervisory Flash */
define exported symbol __cy_memory_2_start    = 0x16000000;
define exported symbol __cy_memory_2_length   = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;

/* XIP */
define exported symbol __cy_memory_3_start    = 0x18000000;
define exported symbol __cy_memory_3_length   = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;

/* eFuse */
define exported symbol __cy_memory_4_start    = 0x90700000;
define exported symbol __cy_memory_4_length   = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;

/* EOF */