/* ** ################################################################### ** Processors: MK66FN2M0VLQ18 ** MK66FN2M0VMD18 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM ** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015 ** Version: rev. 3.0, 2015-03-25 ** Build: b170214 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** o Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** o Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** ################################################################### */ define symbol __ram_vector_table__ = 1; if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } define symbol __stack_size__=MBED_CONF_TARGET_BOOT_STACK_SIZE; define symbol __heap_size__=0x10000; if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0; } if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; } define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; define symbol m_interrupts_start = MBED_APP_START; define symbol m_interrupts_end = MBED_APP_START + 0x3FF; define symbol m_flash_config_start = MBED_APP_START + 0x400; define symbol m_flash_config_end = MBED_APP_START + 0x40F; define symbol m_text_start = MBED_APP_START + 0x410; define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1; define symbol m_interrupts_ram_start = 0x1FFF0000; define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__; define symbol m_crash_data_start = m_interrupts_ram_start + __ram_vector_table_size__; define symbol m_crash_data_size = 0x100; define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__ + m_crash_data_size; define symbol m_data_end = 0x1FFFFFFF; define symbol m_data_2_start = 0x20000000; define symbol m_data_2_end = 0x2002FFFF; /* Sizes */ if (isdefinedsymbol(__stack_size__)) { define symbol __size_cstack__ = __stack_size__; } else { define symbol __size_cstack__ = 0x0400; } if (isdefinedsymbol(__heap_size__)) { define symbol __size_heap__ = __heap_size__; } else { define symbol __size_heap__ = 0x0400; } define exported symbol __VECTOR_TABLE = m_interrupts_start; define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; define exported symbol __CRASH_DATA_RAM_START__ = m_crash_data_start; define exported symbol __CRASH_DATA_RAM_END__ = m_crash_data_start + m_crash_data_size; define memory mem with size = 4G; define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] | mem:[from m_text_start to m_text_end]; define region DATA_region = mem:[from m_data_start to m_data_end] | mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; define block CSTACK with alignment = 8, size = __size_cstack__ { }; define block HEAP with alignment = 8, size = __size_heap__ { }; define block RW { readwrite }; define block ZI { zi }; initialize by copy { readwrite, section .textrw }; do not initialize { section .noinit }; place at address mem: m_interrupts_start { readonly section .intvec }; place in m_flash_config_region { section FlashConfig }; place in TEXT_region { readonly }; place in DATA_region { block RW }; place in DATA_region { block ZI }; place in DATA_region { last block HEAP }; place in CSTACK_region { block CSTACK }; place in m_interrupts_ram_region { section m_interrupts_ram };