#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4

/*
 * Copyright (c) 2020, Nuvoton Technology Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include "../M451_mem.h"

#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
#  if defined(MBED_BOOT_STACK_SIZE)
#    define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
#  else
#    define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#  endif
#endif

#define VECTOR_SIZE                 (4*(16 + 64))

LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {
  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
   *(RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }

  ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_CONF_TARGET_BOOT_STACK_SIZE {
  }

  /* VTOR[TBLOFF] alignment requires:
   *
   * 1. Minumum 32-word
   * 2. Rounding up to the next power of two of table size
   */
  ER_IRAMVEC  AlignExpr(+0, 512)  EMPTY  VECTOR_SIZE  {  ; Reserve for vectors
  }

  RW_IRAM1  AlignExpr(+0, 16)  {  ; 16 byte-aligned
   .ANY (+RW +ZI)
  }

  ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
  }
}

ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))