/* ** ################################################################### ** Processors: LPC54114J256BD64_M4 ** LPC54114J256UK49_M4 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM ** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 ** Version: rev. 1.0, 2016-04-29 ** Build: b161227 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** ** Copyright (c) 2016 Freescale Semiconductor, Inc. ** Copyright 2016 - 2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** o Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** o Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** ################################################################### */ define symbol __ram_vector_table__ = 1; if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } define symbol __stack_size__=MBED_CONF_TARGET_BOOT_STACK_SIZE; define symbol __heap_size__=0x4000; define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x000000E0 : 0; define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000000DF : 0; define symbol m_interrupts_start = 0x00000000; define symbol m_interrupts_end = 0x000000DF; define symbol m_text_start = 0x000000E0; define symbol m_text_end = 0x0002FFFF; define symbol m_interrupts_ram_start = 0x20000000; define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__; define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; define symbol m_data_end = 0x2000FFFF; define exported symbol rpmsg_sh_mem_start = 0x20026800; define exported symbol rpmsg_sh_mem_end = 0x20027FFF; define symbol m_sramx_start = 0x04000000; define symbol m_sramx_end = 0x04007FFF; define exported symbol core1_image_start = 0x00030000; define exported symbol core1_image_end = 0x0003FFFF; define symbol __crp_start__ = 0x000002FC; define symbol __crp_end__ = 0x000002FF; define symbol __ram_iap_start__ = 0x2000FFE0; define symbol __ram_iap_end__ = 0x2000FFFF; /* Sizes */ if (isdefinedsymbol(__stack_size__)) { define symbol __size_cstack__ = __stack_size__; } else { define symbol __size_cstack__ = 0x0400; } if (isdefinedsymbol(__heap_size__)) { define symbol __size_heap__ = __heap_size__; } else { define symbol __size_heap__ = 0x0800; } define exported symbol __VECTOR_TABLE = m_interrupts_start; define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; define memory mem with size = 4G; define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] | mem:[from m_text_start to m_text_end] - mem:[from __crp_start__ to __crp_end__]; define region DATA_region = mem:[from m_data_start to m_data_end] - mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_end__]; define region CSTACK_region = mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_start__-1]; define region SRAMX_region = mem:[from m_sramx_start to m_sramx_end]; define region CRP_region = mem:[from __crp_start__ to __crp_end__]; define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; define block CSTACK with alignment = 8, size = __size_cstack__ { }; define block HEAP with alignment = 8, size = __size_heap__ { }; define block RW { readwrite }; define block ZI { zi }; define region core1_region = mem:[from core1_image_start to core1_image_end]; define block SEC_CORE_IMAGE_WBLOCK { section __sec_core }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) { // Required in a multi-threaded application initialize by copy with packing = none { section __DLIB_PERTHREAD }; } do not initialize { section .noinit }; do not initialize { section rpmsg_sh_mem_section }; place at address mem: m_interrupts_start { readonly section .intvec }; place in TEXT_region { readonly }; place in DATA_region { block RW }; place in DATA_region { block ZI }; place in DATA_region { last block HEAP }; place in SRAMX_region { section sramx }; place in CSTACK_region { block CSTACK }; place in CRP_region { section .crp }; place in m_interrupts_ram_region { section m_interrupts_ram }; place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; place in core1_region { block SEC_CORE_IMAGE_WBLOCK };