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mbed-os / targets / TARGET_STM / TARGET_STM32L4 / TARGET_STM32L475xG / TOOLCHAIN_ARM / stm32l475xg.sct
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; Scatter-Loading Description File
;
; SPDX-License-Identifier: BSD-3-Clause
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2016-2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;*                        opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************

#include "../cmsis_nvic.h"

#if !defined(MBED_APP_START)
  #define MBED_APP_START  MBED_ROM_START
#endif

#if !defined(MBED_APP_SIZE)
  #define MBED_APP_SIZE  MBED_ROM_SIZE
#endif

#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if defined(MBED_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
#else
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
#endif

/* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)


; Crash report enabled as default
#if !defined(MBED_CRASH_REPORT_RAM_SIZE)
#define MBED_CRASH_REPORT_RAM_SIZE  0x100
#endif

;Vectors + Crash report - Fixed at start of RAM2 in sequence
#define MBED_IRAM2_SIZE             (MBED_RAM1_SIZE - VECTORS_SIZE - MBED_CRASH_REPORT_RAM_SIZE)

#define MBED_CRASH_REPORT_RAM_START (MBED_RAM1_START + VECTORS_SIZE)
#define MBED_IRAM2_START            (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)

; Minimum heap should be larger then smallest RAM bank (else can use 
; that bank for heap) and less then largest RAM bank.
#define MINIMUM_HEAP                0x12000

;Splitting the RW and ZI section in IRAM1 (MBED_RAM_SIZE-MINIMUM_HEAP = 0x6000 available)
;and IRAM2 (MBED_IRAM2_SIZE = 0x7D78 available)
LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {    ; load region size_region

  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
  }

  RW_m_crash_data  MBED_CRASH_REPORT_RAM_START  EMPTY  MBED_CRASH_REPORT_RAM_SIZE { ; RW data
  }

  RW_IRAM1  MBED_RAM_START  (MBED_RAM_SIZE - MINIMUM_HEAP)  {  ; RW data
   .ANY (+RW +ZI)
  }

  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))  {
  }

  RW_IRAM2  MBED_IRAM2_START  MBED_IRAM2_SIZE  {
   .ANY (+RW +ZI)
  }

  ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; stack
  }
}