Merge pull request #12615 from jeromecoutant/PR_FPGA_UART
FPGA UART test cases addition with 7 and 9 bits data length
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commit 698fc09b4c70ba8270fa6c9092b2fd3ed6af0e53
2 parents f858000 + 1a64d6e
@Martin Kojtal Martin Kojtal authored on 10 Jun 2020
GitHub committed on 10 Jun 2020
Showing 5 changed files
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TESTS/configs/fpga.json
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TESTS/mbed_hal_fpga_ci_test_shield/README.md 0 → 100644
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TESTS/mbed_hal_fpga_ci_test_shield/fpga_test_shield.jpg 0 → 100644
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TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp
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targets/targets.json