LXT/HXT are external crystl oscillator and can be absent on custom board.
This enables configuring LXT/HXT presence:
1.  By default, LXT/HXT are configured to be present, except M252 which has no HXT.
2.  When LXT is configured to not present, lp_ticker/watchdog will clock by LIRC instead.
3.  Limitations:
    (1) On all targets, LIRC-clocked lp_ticker gets inaccurate and fails to pass tests.
    (2) On NUC472/M453, HIRC-clocked PLL doesn't output 1MHz-aligned frequency. us_ticker gets slight inaccurate.
    (3) On all targets, LIRC-clocked RTC is not supported due to no H/W path/RTC clock source reset to LXT on reset/RTC not trimmed for other clock rates.
4.  On M263, TRNG's clock source defaults to LXT and needs special handling without LXT.
5.  On M252, replace target.hxt-enable with target.hxt-present for consistency.

1. Rephrase the comment
2. Pass WDT reset reason test

Nuvoton: Enlarge NuMaker PWM duty cycle range

These are not used on Mbed OS. Remove them to avoid name conflict with other modules.

Workaround a bug where the boot stack size configuration option is not
passed on to armlink, the Arm Compiler's linker. Prefer
MBED_CONF_TARGET_BOOT_STACK_SIZE if present, as this is what the
configuration system should provide. Fall back to MBED_BOOT_STACK_SIZE
if MBED_CONF_TARGET_BOOT_STACK_SIZE is not defined, as in the case of
buggy tools. If both MBED_CONF_TARGET_BOOT_STACK_SIZE and
MBED_BOOT_STACK_SIZE are not defined, then we fall back to a hard-coded
value provided by the linkerscript. See
https://github.com/ARMmbed/mbed-os/issues/13474 for more information.

To allow overriding of the boot stack size from the Mbed configuration
system, consistently use MBED_CONF_TARGET_BOOT_STACK_SIZE rather than
MBED_BOOT_STACK_SIZE.

Fixes #10319

Relevant modifications:
1. Support degrading QSPI0/1 to SPI4/5 for normal SPI transfer
2. Fix with BSP crypto driver API change
3. Fix with BSP PDMA driver API change
4. Make necessary modifications to pass FPGA CI Test Shield tests
5. Don't distinguish pinmap among parts e.g. M480 LG. Application users must take care.

This is to support custom targets based on M480 series chips.

This is to support custom targets based on M480 series chips.

This is to guarantee SRAM bank2, not initialized yet, isn't used for stack by function preamble code at the very start.

Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST. )

This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.

Add a "used" attribute to Reset_Handler_Cascade to fix GCC build with
the "-flto" flag.
This attribute, attached to a function, means that code must be emitted
for the function even if it appears that the function is not referenced.

On IAR, configure heap to 1KiB at a minimum and expandable, dependent on available SRAM. This requires IAR 8.x.

Support targets:
-   NUMAKER_PFM_NUC472 w/ and w/o XRAM
-   NUMAKER_PFM_M453
-   NUMAKER_PFM_M487/NUMAKER_IOT_M487
-   NUMAKER_IOT_M263A
-   NUMAKER_M252KG

Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts

--legacyalign, --no_legacyalign are deprecated from ARMC6 compiler, in order to
remove deprecated flags all linker files (GCC and IAR as well to have uniformity)
should strictly align to 8-byte boundary