Add Wio-H725AE (#133) ...

* Add clock settings for H725xE

* Correction of memory mapping for H725xE

* Added new target WIO_H725AE

* Added WIO_H725 into targets.json

* Added upload methods file for WIO_H725

* Licence filled from original source file

* Space alignment

* Added macro MBED_SPLIT_HEAP for MCU_STM32H725xE

* Typo correction

* Correction of upload methods for WIO_H725AE

Merge upstream changes into mbed-ce (#117) ...

* Fix for calculating CAN timing settings.

NominalPrescaler value needs to be as high as possible to ensure a good approximation of the target CAN speed.
Previous usage of macro IS_FDCAN_DATA_TSEG1 refers to (unsupported by Mbed ) FDCAN CAN controller settings and leads to too low prescaler values.
Usage Macro IS_FDCAN_NOMINAL_TSEG1 yields optimum results.
See also correct macro usage in line #158.

* Add complete support of DHCP relay interface ID option

RFC3315 specifies the following: "The relay agent MAY send the Interface-id
option to identify the interface on which the client message was received.
If a relay agent  receives a Relay-reply message with an Interface-id
option, the relay agent relays the message to the client through the
interface identified by the option."

The current implementation of the DHCP relay reply handling, the interface
ID field from the server response is ignored. Managing the interface ID
is very important especially as DHCP requests/replies use link-local
addresses. The consequence of this is that the interface must always be
specified because the routing layer cannot guess the correct interface.
Moreover, Mbed provides a mechanism to enable/disable the interface ID
option on a DHCP relay instance, so it is important to fully support it.

The reason why this issue has not been discoverd until now is that the DHCP
relay is mainly used on systems that use only one interface (such as Wi-SUN
routers). By default, when no interface ID is specified for the socket, the
latter will choose 6loWPAN interface by default. This means that if two
interfaces are used on the same device, the 6loWPAN interface is always
selected.

The commit adds code to retrieve the interface-id value contained within
the DHCP relay reply message and write it to a control message header
that is added to the socket message. This tells the socket which
interface to choose. If the interface-id option is not enabled on the
relay, this procedure is simply ignored.

* Support Nuvoton target NUMAKER_IOT_M467

1.  Based on alpha version BSP (85564a2)
2.  Continuing above, tweak BSP:
    (1) Add EPWM_ConfigOutputChannel2() to enable below 1Hz and below 1% duty cycle for PWM output (m460_epwm.h/c).
    (2) Add dummy RTC_WaitAccessEnable() for consistency with previous ports (m460_rtc.h).
3.  Target NuMaker-M467HJ V0.1 board temporarily
4.  Support Arduino UNO form factor for NUMAKER_IOT_M467 target
5.  Enable export to Keil/IAR project
    -   tools/arm_pack_manager/index.json
    -   tools/export/iar/iar_definitions.json

* M467: Fix Greentea reset_reason test failure

HRESETRF is combined reset flag. Filter it out to avoid interference with reset reason check.

* M467: Support HyperRAM

1.  For GCC, support multi-block .data/.bss initialization
2.  HyperRAM is mapped to two regions: 0x0A000000 and 0x80000000
    According to default system address map, 0x0A000000 is located at 'Code' region and 0x80000000 at 'RAM' region.
    With MPU enabled on Mbed OS, 'Code' region is write-never and 'RAM' region execute-never.
    0x80000000 is chosen because 'RAM' regioin is naturally for HyperRAM.
3.  Configurable multi-function pins for HBI
4.  To locate code/data at external HyperRAM:
    -   Specify __attribute__((section(".text.nu.exthyperram"))) for RO/.text/readonly section type
        Invoke mbed_mpu_manager_lock_ram_execution()/mbed_mpu_manager_unlock_ram_execution() to run HyperRAM code
    -   Specify __attribute__((section(".data.nu.exthyperram"))) for RW/.data/readwrite section type
    -   Specify __attribute__((section(".bss.nu.exthyperram"))) for ZI/.bss/zeroinit section type
5.  Add readme

* Config for M460 EMAC

* Add M460 EMAC driver

* Adjust M460 EMAC RX/TX buffer

* M467: Fix EMAC compile error with IAR

* M467: Support Crypto SHA/ECC H/W

1.  Prepare crypto common code
2.  Support list
    -   SHA
    -   ECC
    NOTE: AES/RSA are to support in other works
    NOTE: Compared to M487, M467's SHA supports context save & restore (DMA Cascade mode) and so no software fallback is needed.
    NOTE: M467's ECC, following M487, goes partial-module replacement and it can just improve primitives e.g. point addition/doubling by 2X,
          and cannot improve high level point multiplication because MbedTLS doesn’t open it.
          To improve performance best, full-module replacement is needed.
    NOTE: Continuing above, add support for Montgomery curve

* M467 H/W AES self-test pass

* M467 Support crypto GCM H/W

* M467: GCM support one simple mode instead of using composite GHASH & CTR MODE

* Update M467 AES-GCM to pass AWS-IoT test

* Update M467 AES-GCM for H/W gcm in-buffer creteria

* M467: Improve Crypto H/W wait helper routine

Add crypto_xxx_wait2 helper routine to replace crypto_xxx_wait for Crypto H/W control

* M467: Seed PRNG with TRNG for SCAP

According to TRM, it is suggested PRNG be seeded by TRNG on every Crypto H/W reset.

* M467: Support Crypto RSA H/W

1.  Crypto RSA H/W supports 1024/2048/3072/4096 key bits. Fall back to software implementation for other key bits.
2.  For decrypt, if MBEDTLS_RSA_NO_CRT isn't defined, go CRT, or normal.
3.  For decrypt, when blinding (f_rng != NULL), enable SCAP mode.
4.  Recover from Crypto RSA H/W failure:
    (1) Enable timed-out wait to escape from RSA H/W trap
    (2) On RSA H/W timeout, stop this RSA H/W operation
    (3) Fall back to S/W implementation on failure

NOTE: RSA 4096 key bits can fail with default mbedtls configuration MBEDTLS_MPI_MAX_SIZE.
      Enlarge MBEDTLS_MPI_MAX_SIZE to 1024 or larger if this feature is required.
NOTE: Fixed in BSP RSA driver, for non-CRT+SCAP mode, temporary buffer for MADDR6 requires to be key length plus 128 bits.
NOTE: Fixed in BSP RSA driver, DMA buffer must be 4-word aligned, or RSA H/W will trap.

* M467 Support crypto AES-CCM H/W with one-shot & cascade mode

* M467: Support Crypto ECC H/W in full-module replacement

1.  Replace ecp.c full-module, and other ec modules dependent on ecp.c (ecdh.c/ecdsa.c/ecjpake.c) will improve followingly.
2.  Recover from Crypto ECC H/W failure:
    (1) Enable timed-out wait to escape from ECC H/W trap
    (2) On ECC H/W timeout, stop this ECC H/W operation
    (3) Fall back to S/W implementation on failure
3.  Support Short Weierstrass curve
4.  Support Montgomery curve
    Montgomery curve has the form: B y^2 = x^3 + A x^2 + x
    (1) In S/W impl, A is used as (A + 2) / 4. Figure out its original value for engine.
        https://github.com/ARMmbed/mbed-os/blob/2eb06e76208588afc6cb7580a8dd64c5429a10ce/connectivity/mbedtls/include/mbedtls/ecp.h#L219-L220
    (2) In S/W impl, B is unused. Actually, B is 1 for Curve25519/Curve448 and needs to configure to engine.
        https://github.com/ARMmbed/mbed-os/blob/2eb06e76208588afc6cb7580a8dd64c5429a10ce/connectivity/mbedtls/include/mbedtls/ecp.h#L221-L222
    (3) In S/W impl, y-coord is absent, but engine needs it. Deduce it from x-coord following:
        https://tools.ietf.org/id/draft-jivsov-ecc-compact-05.html
        https://www.rieselprime.de/ziki/Modular_square_root
    NOTE: Fix Curve448 has wrong order value
          https://github.com/Mbed-TLS/mbedtls/pull/5811

* M467: Disable SCAP in RSA H/W

This is to follow designer's resolution.

* M467: support fullspeed usb device

* M467: Fix mbedtls_ecp_point_cmp() call with null argument

Guard from null argument passed to mbedtls_ecp_point_cmp() in ECC H/W port

* M467: Make mbedtls H/W port removable

Some M460 chips don't support AES/SHA/ECC/RSA H/W.
Make them removable from mbedtls H/W port through '"target.macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"]'.

* Added TMPM4NR Platform

New Platform for Toshiba Added

* Removed UTF8 Chars

* M467: I2C: Fix potential role switch failure

Fix in i2c_do_trsn(), interrupt doesn't change back to enabled due to premature return.

* M467: Exclude UNO SPI pins from FPGA CI Test Shield test

UNO D8/D9/D10/D11/D12/D13 can wire to on-board SPI flash.
Exclude these pins from FPGA CI Test Shield test.

* M467: Adjust UART pinmap to pass FPGA CI Test Shield test

* M467: Support NuMaker-IoT-M467 board

Pinout comparison between NuMaker-M467HJ and NuMaker-IoT-M467 boards:
1.  UNO are unchanged
2.  LEDs are unchanged
3.  Buttons are unchanged, except button names
4.  NuMaker-M467HJ has HBI but NuMaker-IoT-M467 does
5.  NuMaker-M467HJ doesn't have ESP8266 but NuMaker-IoT-M467 does
6.  SDHC are unchanged

* Nuvoton: I2C: Fix potential role switch failure

Fix in i2c_do_trsn(), interrupt doesn't change back to enabled due to premature return.

Fix targets:
-   NUMAKER_PFM_NANO130
-   NUMAKER_PFM_NUC472
-   NUMAKER_PFM_M453
-   NUMAKER_PFM_M487/NUMAKER_IOT_M487
-   NUMAKER_IOT_M252
-   NUMAKER_IOT_M263A
-   NU_M2354

* Update can_api.c

Modified comment as discussed.

* M467: Remove invalid UTF-8 byte sequence

* Replace MAX32660, MAX32670 I2C driver with final one in MSDK
- apply clang-format
- Fix i2c repeated start issue

Signed-off-by: Sadik.Ozer <sadik.ozer@analog.com>

* Add proper support for NUCLEO-H723ZG.

- add board specific EMAC setup to connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7
  - stm32h7_eth_init.c was derived from the NUCLEO-H743ZI2 code whilst comparing to the output of STM32CubeIDE
- complete board specific code in targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG
  - PeripheralPins.c and PinNames.h were created by targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py
  - ST ZIO connector pins in PinNames.h have been adapted from NUCLEO-H743ZI2
  - CONSOLE_TX and CONSOLE_RX have been interchanged in PinNames.h to match the actual board layout
  - startup_stm32h723xx.S was derived from startup_stm32h743xx.S
  - stm32h723xg.ld was completely rewritten to match the actual MCU including:
    - split heap support
    - SRAM2 and SRAM4 support
    - crash dump support
    - proper use of DTCM as stack
  - system_clock.c has been changed to support the maximal main clock speed of 550 MHz
- fix handling of HS in FS mode for the target board in targets/TARGET_STM/USBPhy_STM32.cpp
- add board definition to targets/targets.json and correct linker setup for the chip

Signed-off-by: Daniel Starke <daniel-email@gmx.net>

* Fix I2C for MCU_STM32H723xG

Add I2C configuration to MCU_STM32H723xG in target.json as suggested by @jeromecoutant.

Signed-off-by: Daniel Starke <daniel-email@gmx.net>

* Correct MAX32620 boards macro for USB library.

* Limit NUCLEO_H723ZG toolchain to GCC_ARM

Limit NUCLEO_H723ZG toolchain to GCC_ARM only.
This is the only toolchain this target has been tested with yet.

Signed-off-by: Daniel Starke <daniel-email@gmx.net>

* M2354 support FS-USBD and update TF-M for USB PHY select

* Rethink STM32 I2C v2 HAL

* Add documentation for I2C_EVENT macros

* Add some additional I2C error codes

* Added TMPM4GR Platform

New Platform for Toshiba Added

* Resolve delimeter issues for target.json

* Fix compile error on static pinmap targets

* github: Fix click version

Signed-off-by: Martin Kojtal <martin.kojtal@arm.com>

Signed-off-by: Sadik.Ozer <sadik.ozer@analog.com>
Signed-off-by: Daniel Starke <daniel-email@gmx.net>
Signed-off-by: Martin Kojtal <martin.kojtal@arm.com>
Co-authored-by: chdelfs <109847651+chdelfs@users.noreply.github.com>
Co-authored-by: YannCharbon <yann.charbon@ik.me>
Co-authored-by: Chun-Chieh Li <ccli8@nuvoton.com>
Co-authored-by: cyliangtw <cyliang@nuvoton.com>
Co-authored-by: Deepak V. Shreshti <DeepakVS@TOSHIBA-TSIP.COM>
Co-authored-by: Martin Kojtal <martin.kojtal@arm.com>
Co-authored-by: Sadik.Ozer <sadik.ozer@analog.com>
Co-authored-by: Daniel Starke <daniel-email@gmx.net>
Co-authored-by: Ahmet Alincak <Ahmet.Alincak@maximintegrated.com>
Co-authored-by: Jamie Smith <smit109@usc.edu>
Co-authored-by: Jamie Smith <jsmith@crackofdawn.onmicrosoft.com>

Rethink STM32 I2C v2 HAL (#78) ...

* Initial attempt at rethinking the STM32 I2C v2 HAL.  Makes single-byte work properly and adds a new 'state' variable to track what the hardware is doing.

* Fix some initial test failures

* Fix incorrect logic

* Fix more incorrect logic

* Tabs to spaces

* Fix repeated starts with single-byte API

* Fix race condition causing stop() after nacked address to sometimes break things

* Fix missed i2c structs that should have been removed

* Fix doing a repeated start from single-byte to transaction API causing I2C peripheral to lock up

* Fix xferOperation being set wrong for repeated starts, causing the peripheral to hang

* Fix race condition with repeated start after single-byte operation

* Fix compilation for targets that use I2C IP v1

* Fix initialization of XferOperation for API v1, optimize stop()

* Remove unneeded line

* Add docs for I2C events

Convert mbed-ble to STATIC

STM32H7: add MCU_STM32H753xI support

STM32H7 : fix I2C5 build error

STM32: increase i2c slave rx limit. ...

Use uint16_t variables for i2c slave_rx_buffer_size and slave_rx_count
variables. This allows to receive more than 255 bytes in slave mode. The
bytes are received one by one in slave mode so there are no hardware
limitations forcing a 1 byte rx count limit.

STM32H7 : remove warning ...

[Warning] stm32h7xx_hal_hrtim.c@1621,21: equality comparison with extraneous parentheses [-Wparentheses-equality]
[Warning] stm32h7xx_hal_hrtim.c@1625,21: equality comparison with extraneous parentheses [-Wparentheses-equality]
[Warning] stm32h7xx_hal_hrtim.c@2238,21: equality comparison with extraneous parentheses [-Wparentheses-equality]
[Warning] stm32h7xx_hal_hrtim.c@2242,21: equality comparison with extraneous parentheses [-Wparentheses-equality]
[Warning] stm32h7xx_hal_hrtim.c@5332,21: equality comparison with extraneous parentheses [-Wparentheses-equality]
[Warning] stm32h7xx_hal_hrtim.c@5767,21: equality comparison with extraneous parentheses [-Wparentheses-equality]
[Warning] stm32h7xx_hal_hrtim.c@5771,21: equality comparison with extraneous parentheses [-Wparentheses-equality]

[Warning] analogin_device.c@63,30: comparison between 'PinName' and 'enum <anonymous>' [-Wenum-compare]

STM32H7 remove non-UTF characters

STM32H743: correct pack manager rom value

STM32: create MCU_STM32H7B3xIQ for custom boards

STM32: create MCU_STM32H735xG for custom boards

STM32H7 add subfamilies for custom boards ...

- STM32H723xG
- STM32H725xE
- STM32H750xB

STM32 SPI : STM32H7 IP is SPI_IP_VERSION_V2

Merge pull request #14895 from AnishKumarHCL/skip_analog_inn ...

ADC: STM32H7: Skip Negative input analog channels (INN)

ADC: STM32H7: Skip Negative input analog channels (INN) ...

Removed INN ADC channels from PeripheralPins.c

Add missing PBL header

Temp portenta add COMPONENT_4343W_FS BLE firmware

Merge pull request #14663 from arduino/whd_patch_portenta ...

Portenta: Add support to generic COMPONENT_WHD

Merge pull request #14808 from affrinpinhero-2356/i2cTimingPerformanceSolved ...

driver/i2c: STM32: I2C performance issue solved.

Merge pull request #14844 from AnishKumarHCL/analogout_free_implementation ...

Analogout free implementation for F4/F7/H7 boards

analogout: STM32: modified analogout_free api ...

removed hardcoded pins, implemented multi channel check
implemented DAC_2 initialization for H7 board
Added  #if defined DAC_CHANNEL_2

analogout: STM32: Implemented analogout_free for STM32H7 series ...

analogout_free implemented with multiple DAC channel usage check.

driver/i2c: STM32: Solves I2C driver performanc issue. ...

This commit solves issue related to i2c driver performance.
With this commit delay in read write when using i2c timing
algorithm is solved. Used flag mechanism which will check
tim reg value and hz passed.

Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>

Provide missing stubs for ARMClang build

Merge pull request #14776 from affrinpinhero-2356/i2c_longTime_Mem_Solve ...

driver/i2c: STM32: I2C memory usage and time delay in read-write solved.

driver/i2c: STM32: Solves excess memory usage issue. ...

This commit solves excess usage of RAM. User can now enable/disable
I2C timing algorithm. Disabling of I2C timing algorithm would
reduce RAM usage.

Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>

STM32H7 CM4: enable ART

STM32H7 CM4: correct FLASH_SIZE ...

FLASH_SIZE_DATA_REGISTER is not accessible by M4,
acces makes a hard fault

Portenta Add cyhal_system.h placeholder to build with new cypress assets