STM32G0: introduce sub family for custom boards ...

STM32G030x8
STM32G041x8
STM32G050x8
STM32G051x8
STM32G061x8
STM32G081xB
STM32G0B0xE
STM32G0B1xE
STM32G0C1xE

STM32U5: generic STM32 driver files update

Allow more target prescaler for LPTIM

STM32 common filess astyle

STM32WL : ADDING STM32 SUPPORT ...

Add code concerning all STM32 platforms

STM32H7: define RCC_LSE_BYPASS to allow using PC_15 as gpio

Add NUCLEO_G031K8 target configuration

STM32L5 : update generic STM files for L5

TARGET_STM: add support of board NUCLEO_G071RB

TARGET_STM: Remove timeout on HSEM. ...

With tickless mechanism hsem can be used for quite a long time
(time to set up PLL clock).
Also, if hsem is held to long, then this is not the current core which is faulty,
but probably the other (the one which hold the HSEM)

targets: DISCO_H747I add support of MBED_TICKLESS

DISCO_H747I Dualcore support ...

Add 2 targets for DISCO_H747I dualcore:
* DISCO_H747I      -> for CM7 core
* DISCO_H747I_CM4  -> for CM4 core

Current restrictions:
* TICKLESS deactivated
* DeepSleep not supported (DeepSleep wrapped to sleep)

Warning: use of the same IP (example I2C1) by both core at the same time is not prevented,
but is strongly not recommended.
Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC.

Warning: Drag and drop of binary to DISCO_H747I will flash CM7.
         In order to flash CM4, one can use STM32 CubeProgrammer tool.

STM32WB : LSI clock selection when LSE is not available

AStyle

Fix problem with low level lp_ticker STM wrapper

STM32L4: update drivers version to CUBE V1.14.0

STM32: lp_ticker optim: initialize handle once only

STM32: lp_ticker optim: remove irq_handler variable

Update comments and fix typo

Update warning now that C++ wrapper is not needed anymore ...

Now we'd rather not use this wrapper and use instead the low level
wrapper implemented in this driver.

Manage lp_ticker delay at low level ...

LP TICKER mbed-os wrapper needs to be disabled as it introduces too much latencies.

LP TICKER wrapper has been disabled and we need to managed the HW constraints at low level:
- main HW constraint is that once the comparator has been programmed once,
driver cannot program it again before CMPOK HW flag is set, which takes about 3 30us cycles.

To make it even more complex, the driver also needs to cope with "LP ticker workaround"

See commit:

LP ticker workaround

    There is an errata in LPTIM specification that explains that CMP Flag
    condition is not an exact match (COUNTER = MATCH) but rather a
    comparison (COUNTER >= MATCH).

Also the disable interrupt is more complete now:
- always check sleep manager status and restore it
- remove irq_handler as comparator is always programed and might get called
eventually when LP TICK is restarted
- reset delayed_prog

Also in set_interrupt, make sure interrupt does not fire early.
If needed, we decide to slightly delay the tick to cope with the HW limitation to
make sure it will fire as soon as HW is capable.

Functions are called under critical section as they may be called from
the IRQ handler now, not only from driver layer.

LP ticker workaround ...

There is an errata in LPTIM specification that explains that CMP Flag
condition is not an exact match (COUNTER = MATCH) but rather a
comparison (COUNTER >= MATCH).

As a consequence the interrupt is firing early than expected when
programing a timestamp after the 0xFFFF wrap-around.

In order to
work-around this issue, we implement the below work-around.
In case timestamp is after the work-around, let's decide to program the
CMP value to 0xFFFF, which is the wrap-around value. There would anyway be
a wake-up at the time of wrap-around to let the OS update the system time.
When the wrap-around interrupt happen, OS will check the current time and
program again the timestamp to the proper value.

NUCLEO_WB55RG: Rework Clock and sleep support ...

- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.

STM32 LPTICKER (LPTIM): correct init execution after bootloader

STM32 LPTIM update for easy maintenance

Merge pull request #8771 from jeromecoutant/PR_LPTICKER_LPTIM ...

STM32 LPTICKER with LPTIM optimisation

STM32 LPTICKER with LPTIM optimisation

STM32 LPTICKER with LPTIM : reduce clock feature

STM32 LPTICKER with RTC : Fix tickless and lp wrapper ...

When both tickless and LPTICKER_DELAY_TICKS are enabled some ST
devices randomly get stuck sleeping forever. This is because the
wake up time passed to the rtc is ignored if the previous match is
about to occur. This causes the device to get stuck in sleep.

This patch prevents matches from getting dropped by the rtc by
deactivating the rtc wake up timer before setting a new value.

Events leading up to this failure for the RTC:

-1st call to lp_ticker_set_interrupt
-delay until ticker interrupt is about to fire
-2nd call to lp_ticker_set_interrupt
-interrupt for 1st call fires and match time for 2nd call is dropped
-LowPowerTickerWrapper gets ticker interrupt but treats it as a
 spurious interrupt and drops it since it comes in too early
-device enters sleep without a wakeup source and locks up

STM32 LPTICKER with LPTIM : Fix tickless and lp wrapper ...

This fixes issue with mbed_hal/lp_ticker/lp_ticker_early_match_race_test