STM32 common filess astyle

STM32WL : ADDING STM32 SUPPORT ...

Add code concerning all STM32 platforms

STM32L4+ : SRAM3 is powered off in Stop 2 mode ...

By default, SRAM3 content is then lost.

Increase MSI clock frequency when exiting deep sleep ...

This will optimize down the time it takes to restore the clock
settings when getting out of deep sleep.

If 48MHz is available let's use it, otherwise at least 4MHz should be
available for any MCU with MSI.

TARGET_STM: Improve H747 dual core Deepsleep robustness

TARGET_STM: Remove timeout on HSEM. ...

With tickless mechanism hsem can be used for quite a long time
(time to set up PLL clock).
Also, if hsem is held to long, then this is not the current core which is faulty,
but probably the other (the one which hold the HSEM)

TARGET_STM: rework hal_sleep management to be compatible with all STM32 families

targets: DISCO_H747I add support of MBED_TICKLESS

DISCO_H747I Dualcore support ...

Add 2 targets for DISCO_H747I dualcore:
* DISCO_H747I      -> for CM7 core
* DISCO_H747I_CM4  -> for CM4 core

Current restrictions:
* TICKLESS deactivated
* DeepSleep not supported (DeepSleep wrapped to sleep)

Warning: use of the same IP (example I2C1) by both core at the same time is not prevented,
but is strongly not recommended.
Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC.

Warning: Drag and drop of binary to DISCO_H747I will flash CM7.
         In order to flash CM4, one can use STM32 CubeProgrammer tool.

NUCLEO_WB55RG: Rework Clock and sleep support ...

- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.

STM32 SLEEP update for easy maintenance

STM32L4 : sleep issue

Merge pull request #7813 from MSiglreithmaierRB/os_sleep_stm32l4 ...

STM32L4: Fix sleep implementation

STM32L4: Use HAL layer functions for sleep implementation

STM: Fix us_ticker timestamp after deep sleep ...

Use the `mbed_sdk_inited` flag to correct the `HAL_GetTick()` behavior
after waking up from deep sleep mode. `ticker_read_us()` must not be
used to read us_ticker timestamp after waking up until the us_ticker
context is restored. More detailed description in issue #8117.

Fixes #8117

STM32L4: Fix sleep implementation ...

Correctly detect and handle the low power run mode when entering and exiting sleep mode.

The generic `hal_sleep` implementation tries to exit LPR mode always, resulting in a spin-loop during a critical section (disabled IRQ).
The new approach returns from LPR to Run mode if enabled (LPR bit set), enters sleep, and resets to the original state on wakeup (WFI).

Use HAL coding style for function naming

STM32: check for UART ongoing transfers before entering deepsleep ...

As suggested by Russ Butler in mbed-os issue #7328, and until there is an
implementation of mbed-os issue #4408, we are implementing a workaround
at HAL level to check if there is any ongoing serial transfer (which happens
if HW FIFO is not yet empty).

In case a transfer is ongoing, we're not entering deep sleep and
return immediately.

Merge pull request #7365 from jeromecoutant/PR_RTC_SHADOW ...

STM32 RTC : bypass shadow registers

stm32 ticker: rename hal_tick.h in us_ticker_data.h

STM32 RTC : bypass shadow registers ...

- RTC_SSR for the subseconds
- RTC_TR for the time
- RTC_DR for the date

These registers were accessed through shadow registers which are synchronized with PCLK1 (APB1 clock).
They are now accessed directly in order to avoid waiting for the synchronization duration.

save/restore timer registers before/after deepsleep

Re-enable IT CC1 after deepsleep

TARGET_STM astyle

STM32: Reduce HAL_deepsleep stack usage ...

There are cases where a call hal_deepsleep would overflow the idle task
stack, especially in developper or debug profile.

In order to avoid this case, we split ForceClockOutofDeepSleep
into two separate functions the two structure RCC_ClkInitStruct and
RCC_OscInitStruct are not allocated at the same time.

Cleanup ...

- Remove calls to HAL_SuspendTick and HAL_ResumeTick
- Rename stm_common.c in hal_tick_common.c

STM32 LPTICKER : clean include file

Style fix

Add delay to let clock stabilize when out of deep sleep ...

Tests have shown that there is hich-up on MSI clock during the setup phase.
If this stabilization phase happens when application has restarted again
this can have side effects, like grambled UART characters typically.

So we're adding a delay before hading-over back to application.

With this modification, on NCULEO_L476RG, the wake-up time is increased
from 2ms to 2,5ms.
If possible this should be improved in the future to save 500 microseconds
of wak-up time.  See TODO

Use temporarily MSI or HSI when exiting Deep Sleep ...

There are cases where HW registers are found in unpexcepted state when
exiting Deep Sleep only few micro-seconds after it was entered.

By using an internal clock that does not depend on anythin and clocking
the system without using PLL, this allows SetSysClock default configuration
to run fine whatever possible configuration we find the HW in when
exiting Deep Sleep.

Also we shall restore interrupts only after all cloks are back to
expected running state.