Fix STM32 SPI async API for STM32H7 (SPI_IP_VERSION_V2) ...

By default, HAL functions (HAL_SPI_TransmitReceive_IT/HAL_SPI_Transmit_IT/HAL_SPI_Receive_IT) assume that SPI is disabled between function invocation.
It's needed to set transfer size (CR2 register), that can be modified only if SPI disabled. But `stm32_spi_api.c` keeps SPI enabled after initialization.

This commit adds helper code for STM32H7 (SPI_IP_VERSION_V2) that disables SPI before HAL_SPI_TransmitReceive_IT/HAL_SPI_Transmit_IT/HAL_SPI_Receive_IT
and after end of transaction for HAL API compatibility.

Fix STM32 SPI 16-bit logic ...

Update SPI logic to process 16 bit words in the same way by sync/async,
3/4 wires modes:
- fix 3-wire synchronous transmission to move 2 or more bytes between buffer and
  SPI register per word tarnsmission
- fix 4-wire synchronous transmission to move 2 or more bytes between buffer and
  SPI register per word tarnsmission

STM32 SPI : Pull Down for output line

STM32 SPI : Add SPI reset in init

STM32 SPI : STM32H7 IP is SPI_IP_VERSION_V2

Improve STM32 SPI asynchronous API stability ...

`HAL_SPI_Receive_IT` HAL function causes dummy reads in 3-wire mode,
that causes data corruption in RX FIFO/register. It isn't possible
to fix it without signification refactoring, but we may prevent data
corruption with the following fixes:

- RX buffer/register cleanup after asynchronous transfer in 3-wire mode
- Explicit RX buffer/register cleanup after SPI initialization
  (for cases if we re-create SPI object).

Fix STM32 spi_abort_asynch function ...

- add RX cleanup after SPI re-initialization,
  as it isn't implemented in the `HAL_SPI_Init`
- cancel SPI enabling for 3-wire mode

Fix STM32 SPI 3-wire (synchronous API) ...

All STM32 families except STM32H7 has the following 3-wire SPI peculiarity in master receive mode:
SPI continuously generates clock signal till it's disabled by a software. It causes that a software
must disable SPI in time. Otherwise, "dummy" reads will be generated.

Current STM32 synchronous SPI 3-wire implementation relies on HAL library functions HAL_SPI_Receive/HAL_SPI_Transmit.
It performs some SPI state checks to detect errors, but unfortunately it isn't fast enough to disable SPI in time.
Additionally, a multithreading environment or interrupt events may cause extra delays.

This commit contains the custom transmit/receive function for SPI 3-wire mode. It uses critical sections to
prevents accidental interrupt event delays, disables SPI after each frame receiving and disables SPI during
frame generation. It adds some delay between SPI frames (~700 ns), but gives reliable 3-wire SPI communications.

Move common STM32 SPI operations to separate functions ...

- move a code that waits readable SPI state from `spi_master_write`
  function to inline functions `msp_writable` and `msp_wait_writable`
- move a code that waits writeable SPI state from `spi_master_write`
  function to inline functions `msp_readable` and `msp_wait_readable`
- move a code that writes data to SPI from `spi_master_write`
  function to inline function `msp_write_data`
- move a code that reads data from SPI from `spi_master_write`
  function to inline function `msp_read_data`

Merge pull request #14699 from jeromecoutant/PR_ASTYLE ...

STM32 astyle format

STM32 common filess astyle

Added information on limitation of asynchronous SPI at high speeds(MHz ...

ranges)

STM32 SPI : correct GPIO free

STM32WL : ADDING STM32 SUPPORT ...

Add code concerning all STM32 platforms

Add SPI bitwidths to ST targets where supported

STM32 warning remove

STM pin_function(), pin_mode(): return immediately when given pin is NC ...

Additionally, remove redundant pin checks against NC when above functions are used.

Allow NC for MISO or MOSI while initializing SPI ...

Static pinmap extension required to use pin_function() and pin_mode() functions instead of pinmap_pinout(). Unfortunatelly pin_function() does not allow passing NC pin.
Call pin_function() and pin_mode() only if MISO/MOSI pin is not NC.

Merge pull request #12153 from mprse/spi_fpga_test_extend ...

Hackathon: Increase coverage of the SPI master FPGA test

STM32L5 : update generic STM files for L5

STM SPI capabilities: rx/tx buffers can have different sizes

Merge pull request #11950 from ABOSTM/DISCO_H747I_TICKLESS ...

DISCO_H747I: add support of MBED_TICKLESS

Change explicit pinmap to static pinmap

STM SPI driver: Add explicit pinmap support

TARGET_STM: Remove timeout on HSEM. ...

With tickless mechanism hsem can be used for quite a long time
(time to set up PLL clock).
Also, if hsem is held to long, then this is not the current core which is faulty,
but probably the other (the one which hold the HSEM)

TARGET_STM: remove warning and fix typo on SPI

DISCO_H747I Dualcore support ...

Add 2 targets for DISCO_H747I dualcore:
* DISCO_H747I      -> for CM7 core
* DISCO_H747I_CM4  -> for CM4 core

Current restrictions:
* TICKLESS deactivated
* DeepSleep not supported (DeepSleep wrapped to sleep)

Warning: use of the same IP (example I2C1) by both core at the same time is not prevented,
but is strongly not recommended.
Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC.

Warning: Drag and drop of binary to DISCO_H747I will flash CM7.
         In order to flash CM4, one can use STM32 CubeProgrammer tool.

Tweak stm_spi_api Coverity issue. ...

Coverity warining: "memset fill truncated (NO_EFFECT)".
Changed SPI_FILL_WORD to SPI_FILL_CHAR.

TARGET_STM: SPI: update pull up config depending on clk polarity ...

Fix #10589

Signed-off-by: Vincent Veron <vincent.veron@st.com>

TARGET_STM: SPI: add pulse on master transmissions ...

Add a pulse when using hardware chip select for SPI transmissions.
CS is at low level when a transmission is on-going.

Be careful, this is not compatible with all modes. It will work only
if PHA is 0, ie spi mode is 0 or 2. See stm32xx reference manual,
chapter "NSS pulse mode" for more details.

Fix #10671

Signed-off-by: Vincent Veron <vincent.veron@st.com>