/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
#include <arch.h>
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
/*******************************************************************************
* Generic platform constants
******************************************************************************/
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x800
/* Size of coherent stacks for debug and release builds */
#if DEBUG
#define PCPU_DV_MEM_STACK_SIZE 0x400
#else
#define PCPU_DV_MEM_STACK_SIZE 0x300
#endif
#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
/* Trusted Boot Firmware BL2 */
#define BL2_IMAGE_NAME "bl2.bin"
/* EL3 Runtime Firmware BL3-1 */
#define BL31_IMAGE_NAME "bl31.bin"
/* SCP Firmware BL3-0 */
#define BL30_IMAGE_NAME "bl30.bin"
/* Secure Payload BL3-2 (Trusted OS) */
#define BL32_IMAGE_NAME "bl32.bin"
/* Non-Trusted Firmware BL3-3 */
#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
/* Firmware Image Package */
#define FIP_IMAGE_NAME "fip.bin"
#define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CORE_COUNT 6
#define PRIMARY_CPU 0x100
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
#define FLASH_BASE 0x08000000
#define FLASH_SIZE 0x04000000
/* Bypass offset from start of NOR flash */
#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
#ifndef TZROM_BASE
/* Use the bypass address */
#define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET
#endif
#define TZROM_SIZE 0x00010000
#define TZRAM_BASE 0x04001000
#define TZRAM_SIZE 0x0003F000
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base
* addresses.
******************************************************************************/
#define BL1_RO_BASE TZROM_BASE
#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
#define BL1_RW_BASE TZRAM_BASE
#define BL1_RW_LIMIT BL31_BASE
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xd000)
#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
* Load address of BL3-0 in the Juno port
* BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the
* SCP, it is discarded and BL3-1 is loaded over the top.
******************************************************************************/
#define BL30_BASE BL31_BASE
/*******************************************************************************
* BL3-1 specific defines.
******************************************************************************/
#define BL31_BASE (TZRAM_BASE + 0x8000)
#define BL31_LIMIT BL32_BASE
/*******************************************************************************
* BL3-2 specific defines.
******************************************************************************/
#define TSP_SEC_MEM_BASE TZRAM_BASE
#define TSP_SEC_MEM_SIZE TZRAM_SIZE
#define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000)
#define BL32_LIMIT BL2_BASE
/*******************************************************************************
* Load address of BL3-3 in the Juno port
******************************************************************************/
#define NS_IMAGE_OFFSET 0xE0000000
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#define MAX_XLAT_TABLES 5
#define MAX_MMAP_REGIONS 16
/*******************************************************************************
* ID of the secure physical generic timer interrupt.
******************************************************************************/
#define IRQ_SEC_PHY_TIMER 29
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define CCI400_BASE 0x2c090000
#define CCI400_SL_IFACE_CLUSTER0 4
#define CCI400_SL_IFACE_CLUSTER1 3
#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
CCI400_SL_IFACE_CLUSTER1 : \
CCI400_SL_IFACE_CLUSTER0)
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#endif /* __PLATFORM_DEF_H__ */
