/*
 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/dts-v1/;

#include "fvp-base-gicv3-psci-common.dtsi"

/* DynamIQ based designs have upto 8 CPUs in each cluster */

&CPU_MAP {
	cluster0 {
		core0 {
			cpu = <&CPU0>;
		};
		core1 {
			cpu = <&CPU1>;
		};
		core2 {
			cpu = <&CPU2>;
		};
		core3 {
			cpu = <&CPU3>;
		};
		core4 {
			cpu = <&CPU4>;
		};
		core5 {
			cpu = <&CPU5>;
		};
		core6 {
			cpu = <&CPU6>;
		};
		core7 {
			cpu = <&CPU7>;
		};
	};
};