DSU: Implement workaround for errata 798953

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LuminaSensum / arm-trusted-firmware

Browse code DSU: Implement workaround for errata 798953 Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2
1 parent 2c3b76c commit 0e985d708e8f429c1fa1f557d3eea90e32de5228 Louis Mayencourt authored on 9 Apr 2019

Browse code

Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.

Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2

1 parent 2c3b76c commit 0e985d708e8f429c1fa1f557d3eea90e32de5228

Louis Mayencourt authored on 9 Apr 2019

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Ignore Space Show notes View docs/cpu-specific-build-macros.rst

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