Tegra194: memctrl: set reorder depth limit for PCIE blocks

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LuminaSensum / arm-trusted-firmware

Browse code Tegra194: memctrl: set reorder depth limit for PCIE blocks HW bug in third party PCIE IP - PCIE datapath hangs when there are more than 28 outstanding requests on data backbone for x1 controller. Suggested SW WAR is to limit reorder_depth_limit to 16 for PCIE 1W/2AW/3W clients. Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067 Signed-off-by: Puneet Saxena <puneets@nvidia.com> WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3
1 parent eb41fee commit 34a6610aeb8e1e976c3afc65155210e919633927 Puneet Saxena authored on 7 Mar 2018 Varun Wadekar committed on 23 Jan 2020

Browse code

HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.

Suggested SW WAR is to limit reorder_depth_limit to 16 for
PCIE 1W/2AW/3W clients.

Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067
Signed-off-by: Puneet Saxena <puneets@nvidia.com>

WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3

1 parent eb41fee commit 34a6610aeb8e1e976c3afc65155210e919633927

Puneet Saxena authored on 7 Mar 2018

Varun Wadekar committed on 23 Jan 2020

Patch

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Ignore Space Show notes View plat/nvidia/tegra/include/t194/tegra_mc_def.h

Ignore Space Show notes View plat/nvidia/tegra/soc/t194/plat_memctrl.c

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