GitBucket
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intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f |
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Abdul Halim, Muhammad Hadi Asyrafi
committed
on 15 Jan 2020
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| plat/intel/soc/agilex/bl2_plat_setup.c |
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| plat/intel/soc/agilex/include/agilex_memory_controller.h |
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| plat/intel/soc/agilex/include/agilex_reset_manager.h |
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| plat/intel/soc/agilex/include/agilex_system_manager.h |
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| plat/intel/soc/agilex/soc/agilex_reset_manager.c |
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| plat/intel/soc/stratix10/bl2_plat_setup.c |
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| plat/intel/soc/stratix10/include/s10_memory_controller.h |
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| plat/intel/soc/stratix10/include/s10_reset_manager.h |
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| plat/intel/soc/stratix10/include/s10_system_manager.h |
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| plat/intel/soc/stratix10/soc/s10_memory_controller.c |
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| plat/intel/soc/stratix10/soc/s10_reset_manager.c |
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