ti: k3: common: Remove coherency workaround for AM65x
We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.

Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>
1 parent 65f7b81 commit 48d6b2643462b43ed617ca3751121a5587881e44
@Andrew F. Davis Andrew F. Davis authored on 25 Apr 2019
John Tsichritzis committed on 6 Jun 2019
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lib/cpus/aarch64/cortex_a53.S
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plat/ti/k3/common/k3_psci.c
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plat/ti/k3/common/plat_common.mk