Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html

Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
1 parent 49d969b commit 5f5d0763875218893d3831a685886c17d20be940
@Andre Przywara Andre Przywara authored on 20 May 2019
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docs/design/cpu-specific-build-macros.rst
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include/lib/cpus/aarch64/neoverse_n1.h
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lib/cpus/aarch64/neoverse_n1.S
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lib/cpus/cpu-ops.mk