Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
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docs/cpu-specific-build-macros.rst |
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include/arch/aarch64/arch.h |
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lib/cpus/aarch64/cortex_a75.S |
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lib/cpus/cpu-ops.mk |
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lib/el3_runtime/aarch64/context_mgmt.c |
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