GitBucket
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Merge changes from topic "tegra-downstream-02182020" into integration
* changes: Tegra186: store TZDRAM base/size to scratch registers Tegra186: add SE support to generate SHA256 of TZRAM Tegra186: add support for bpmp_ipc driver Tegra210: disable ERRATA_A57_829520 Tegra194: memctrl: add support for MIU4 and MIU5 Tegra194: memctrl: remove support to reconfigure MSS Tegra: fiq_glue: remove bakery locks from interrupt handler Tegra210: SE: add context save support Tegra210: update the PMC blacklisted registers Tegra: disable CPUACTLR access from lower exception levels cpus: denver: fixup register used to store return address |
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TrustedFirmware Code Review
committed
on 10 Mar 2020
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| lib/cpus/aarch64/denver.S |
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| plat/nvidia/tegra/common/aarch64/tegra_helpers.S |
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| plat/nvidia/tegra/common/tegra_fiq_glue.c |
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| plat/nvidia/tegra/include/drivers/pmc.h |
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| plat/nvidia/tegra/include/drivers/security_engine.h |
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| plat/nvidia/tegra/include/t186/tegra_def.h |
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| plat/nvidia/tegra/include/t210/tegra_def.h |
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| plat/nvidia/tegra/soc/t186/drivers/se/se.c 0 → 100644 |
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| plat/nvidia/tegra/soc/t186/drivers/se/se_private.h 0 → 100644 |
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| plat/nvidia/tegra/soc/t186/plat_memctrl.c |
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| plat/nvidia/tegra/soc/t186/plat_psci_handlers.c |
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| plat/nvidia/tegra/soc/t186/plat_setup.c |
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| plat/nvidia/tegra/soc/t186/platform_t186.mk |
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| plat/nvidia/tegra/soc/t194/plat_memctrl.c |
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| plat/nvidia/tegra/soc/t210/drivers/se/se_private.h |
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| plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c |
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| plat/nvidia/tegra/soc/t210/plat_psci_handlers.c |
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| plat/nvidia/tegra/soc/t210/plat_setup.c |
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| plat/nvidia/tegra/soc/t210/plat_sip_calls.c |
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| plat/nvidia/tegra/soc/t210/platform_t210.mk |
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