ti: k3: common: Do not disable cache on TI K3 core powerdown
Leave the caches on and explicitly flush any data that may be stale when the core is powered down. This prevents non-coherent interconnect access which has negative side- effects on AM65x. Signed-off-by: Andrew F. Davis <afd@ti.com> |
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lib/cpus/aarch64/cortex_a53.S |
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plat/ti/k3/common/k3_psci.c |
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plat/ti/k3/common/plat_common.mk |
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