GitBucket
|
intel: agilex: Clear PLL lostlock bypass mode
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1 |
|---|
|
|
| plat/intel/soc/agilex/include/agilex_clock_manager.h |
|---|
| plat/intel/soc/agilex/soc/agilex_clock_manager.c |
|---|