GitBucket
|
plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677 |
|---|
|
Manish Pandey
committed
on 8 Jun 2020
|
| plat/intel/soc/agilex/bl2_plat_setup.c |
|---|
| plat/intel/soc/agilex/include/agilex_clock_manager.h |
|---|
| plat/intel/soc/agilex/include/agilex_mmc.h 0 → 100644 |
|---|
| plat/intel/soc/agilex/platform.mk |
|---|
| plat/intel/soc/agilex/soc/agilex_mmc.c 0 → 100644 |
|---|
| plat/intel/soc/common/include/socfpga_system_manager.h |
|---|