Tegra: support to set the L2 ECC and Parity enable bit

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LuminaSensum / arm-trusted-firmware

Browse code Tegra: support to set the L2 ECC and Parity enable bit This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1
1 parent 322e7c3 commit b495791ba28ae36078e09d32877fca8e97088410 Harvey Hsieh authored on 23 Nov 2016 Varun Wadekar committed on 16 Jan 2019

Browse code

This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.

* with some coverity fix:
MISRA C-2012 Directive 4.6
MISRA C-2012 Rule 2.5
MISRA C-2012 Rule 10.3
MISRA C-2012 Rule 10.4

Change-Id: Id7303bbbdc290b52919356c31625847b8904b073
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1

1 parent 322e7c3 commit b495791ba28ae36078e09d32877fca8e97088410

Harvey Hsieh authored on 23 Nov 2016

Varun Wadekar committed on 16 Jan 2019

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Ignore Space Show notes View docs/plat/nvidia-tegra.rst

Ignore Space Show notes View plat/nvidia/tegra/common/aarch64/tegra_helpers.S

Ignore Space Show notes View plat/nvidia/tegra/common/tegra_bl31_setup.c

Ignore Space Show notes View plat/nvidia/tegra/include/tegra_private.h

Ignore Space Show notes View plat/nvidia/tegra/soc/t186/plat_psci_handlers.c

Ignore Space Show notes View plat/nvidia/tegra/soc/t186/plat_setup.c

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