Cortex-A35: Implement workaround for errata 855472

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Browse code Cortex-A35: Implement workaround for errata 855472 Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2
1 parent 5d149bd commit cba71b70ef7070bcd38a8d202f30e58f79e36c6b Louis Mayencourt authored on 5 Apr 2019

Browse code

Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.

Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2

1 parent 5d149bd commit cba71b70ef7070bcd38a8d202f30e58f79e36c6b

Louis Mayencourt authored on 5 Apr 2019

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Ignore Space Show notes View docs/cpu-specific-build-macros.rst

Ignore Space Show notes View include/lib/cpus/aarch64/cortex_a35.h

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