Add memory barriers to ensure that all translation table writes
have drained into memory, the TLB invalidation is complete,
and translation register writes are committed before enabling
the MMU.

Also ensure the MMU enable takes effect immediately.

These changes are necessary because of commit 8cec598ba3b6.

Change-Id: I65b5c3593af27f19da3fd2170c55f631f1ce7b81