Workaround for Cortex A76 erratum 1800710
Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493 |
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docs/design/cpu-specific-build-macros.rst |
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include/lib/cpus/aarch64/cortex_a76.h |
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lib/cpus/aarch64/cortex_a76.S |
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lib/cpus/cpu-ops.mk |
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