Disable processor Cycle Counting in Secure state
In a system with ARMv8.5-PMU implemented:

- If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting
  in Secure state in PMCCNTR.

- If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in
  Secure state in PMCCNTR_EL0.

So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64)
or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure
as any EL can change that value.

Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
1 parent fa233ac commit ed4fc6f026999daad19b4bb47e6b6626078206c2
@Antonio Nino Diaz Antonio Nino Diaz authored on 18 Feb 2019
Showing 4 changed files
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include/arch/aarch32/arch.h
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include/arch/aarch32/el3_common_macros.S
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include/arch/aarch64/arch.h
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include/arch/aarch64/el3_common_macros.S