arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.

This patch adds Virtual QEMU platform support for
this SoC "versal_virt".

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
1 parent 3c1fb7a commit f91c3cb1df7d41122185063453f39dfe90119b5b
@Siva Durga Prasad Paladugu Siva Durga Prasad Paladugu authored on 25 Sep 2018
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docs/plat/xilinx-versal.md 0 → 100644
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plat/xilinx/versal/aarch64/versal_common.c 0 → 100644
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plat/xilinx/versal/aarch64/versal_helpers.S 0 → 100644
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plat/xilinx/versal/bl31_versal_setup.c 0 → 100644
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plat/xilinx/versal/include/plat_macros.S 0 → 100644
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plat/xilinx/versal/include/platform_def.h 0 → 100644
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plat/xilinx/versal/plat_psci.c 0 → 100644
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plat/xilinx/versal/plat_topology.c 0 → 100644
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plat/xilinx/versal/plat_versal.c 0 → 100644
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plat/xilinx/versal/platform.mk 0 → 100644
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plat/xilinx/versal/sip_svc_setup.c 0 → 100644
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plat/xilinx/versal/versal_def.h 0 → 100644
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plat/xilinx/versal/versal_gicv3.c 0 → 100644
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plat/xilinx/versal/versal_private.h 0 → 100644