LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-01-21	004c922 Browse files » Merge changes Ib1ed9786,I6c4855c8 into integration ... * changes: plat: imx: Correct the SGIs that used for secure interrupt plat: imx8mm: Add the support for opteed spd on imx8mq/imx8mm Sandrine Bailleux authored on 21 Jan 2020 TrustedFirmware Code Review committed on 21 Jan 2020
2020-01-21	3b3d406 Browse files » Merge "docs: Add upcoming Change Log to Table of Contents" into integration Sandrine Bailleux authored on 21 Jan 2020 TrustedFirmware Code Review committed on 21 Jan 2020
2020-01-20	7b78789 Browse files » Merge changes from topic "tegra-downstream-01082020" into integration ... * changes: Tegra194: platform handler for entering CPU standby state Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent Tegra194: memctrl: fix bug in client order id reg value generation Tegra194: memctrl: enable mc coalescer Tegra194: update scratch registers used to read boot parameters Tegra194: implement system shutdown/reset handlers Tegra194: mce: support for shutdown and reboot Tegra194: request CG7 before checking if SC7 is allowed Tegra194: config to enable/disable strict checking mode Tegra194: remove unused platform configs Tegra194: restore XUSB stream IDs on System Resume Manish Pandey authored on 20 Jan 2020 TrustedFirmware Code Review committed on 20 Jan 2020
	7b3ab4e Browse files » Merge "plat: xilinx: zynqmp: Add checksum support for IPI data" into integration Manish Pandey authored on 20 Jan 2020 TrustedFirmware Code Review committed on 20 Jan 2020
	7ae80e5 Browse files » Merge "zynqmp: pm_service: Add support to query max divisor" into integration Manish Pandey authored on 20 Jan 2020 TrustedFirmware Code Review committed on 20 Jan 2020
	24d7deb Browse files » Merge "rpi3/4: Add support for offlining CPUs" into integration Manish Pandey authored on 20 Jan 2020 TrustedFirmware Code Review committed on 20 Jan 2020
	0a91095 Browse files » Merge changes from topic "ld/mtd_framework" into integration ... * changes: doc: stm32mp1: Update build command line fdts: stm32mp1: remove second QSPI flash instance stm32mp1: Add support for SPI-NOR boot device stm32mp1: Add support for SPI-NAND boot device spi: stm32_qspi: Add QSPI support fdts: stm32mp1: update for FMC2 pin muxing stm32mp1: Add support for raw NAND boot device fmc: stm32_fmc2_nand: Add FMC2 driver support stm32mp1: Reduce MAX_XLAT_TABLES to 4 io: stm32image: fix device_size type stm32mp: add DT helper for reg by name stm32mp1: add compilation flags for boot devices lib: utils_def: add CLAMP macro compiler_rt: Import popcountdi2.c and popcountsi2.c files Add SPI-NOR framework Add SPI-NAND framework Add SPI-MEM framework Add raw NAND framework Soby Mathew authored on 20 Jan 2020 TrustedFirmware Code Review committed on 20 Jan 2020
	ac7764b Browse files » doc: stm32mp1: Update build command line ... Add new flags for storage support that must be used in the build command line. Add the complete build steps for an OP-TEE configuration. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I0c682f6eb0aab83aa929f4ba734d3151c264aeed Lionel Debieve committed on 20 Jan 2020
	46e9b7a Browse files » fdts: stm32mp1: remove second QSPI flash instance ... Remove second flash node as only one must be used by QSPI NOR driver. Change-Id: I48189f2fdf4e0455aabe7d4cd9b2f3d36bb9cfb5 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
	b1b218f Browse files » stm32mp1: Add support for SPI-NOR boot device ... STM32MP1 platform is able to boot from SPI-NOR devices. These modifications add this support using the new SPI-NOR framework. Change-Id: I75ff9eba4661f9fb87ce24ced2bacbf8558ebe44 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
	5704422 Browse files » stm32mp1: Add support for SPI-NAND boot device ... STM32MP1 platform is able to boot from SPI-NAND devices. These modifications add this support using the new SPI-NAND framework. Change-Id: I0d5448bdc4bde153c1209e8043846c0f935ae5ba Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
	0581a88 Browse files » spi: stm32_qspi: Add QSPI support ... Add QSPI support (limited to read interface). Implements the memory map and indirect modes. Low level driver based on SPI-MEM operations. Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Lionel Debieve committed on 20 Jan 2020
	7e51e88 Browse files » fdts: stm32mp1: update for FMC2 pin muxing ... Include the required FMC2 pinmux definition for the NAND management. Change-Id: I80333deacdf3444b2f21f17f2fb5919e569a3591 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
	12e21df Browse files » stm32mp1: Add support for raw NAND boot device ... STM32MP1 platform is able to boot from raw NAND devices. These modifications add this support using the new raw NAND framework. Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
	695f7df Browse files » fmc: stm32_fmc2_nand: Add FMC2 driver support ... Add fmc2_nand driver support. The driver implements only read interface for NAND devices. Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Lionel Debieve committed on 20 Jan 2020
	e98f594 Browse files » stm32mp1: Reduce MAX_XLAT_TABLES to 4 ... For STM32MP1, the address space is 4GB, which can be first divided in 4 parts of 1GB. This LVL1 table is already mapped regardless of MAX_XLAT_TABLES. Fixing typo: Replace Ko to KB. BL2/sp_min for platform STM32MP1 requires 4 MMU translation tables: - a level2 table and a level3 table for identity mapped SYSRAM - a level2 table mapping 2MB of BootROM runtime resources - a level2 table mapping 2MB of secure DDR (case BL32 is OP-TEE) Change-Id: If80cbd4fccc7689b39dd540d6649b1313557f326 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Nicolas Le Bayon authored on 27 Sep 2019 Lionel Debieve committed on 20 Jan 2020
	b8718d1 Browse files » io: stm32image: fix device_size type ... Device size could be more than 4GB, we must define size as unsigned long long. Change-Id: I52055cf5c1c15ff18ab9e157aa9b73c8b4fb7b63 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
	dd85e57 Browse files » stm32mp: add DT helper for reg by name ... Add a new entry to find register properties by name and include new assert functions to limit address cells to 1 and size cells to 1. Change-Id: Ide59a795a05fb2af36bd07fec15e5a3adf196226 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
	46554b6 Browse files » stm32mp1: add compilation flags for boot devices ... Adds compilation flags to specify which drivers will be embedded in the generated firmware. Change-Id: Ie9decc89c3f26cf17e7148a3a4cf337fd35940f7 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Nicolas Le Bayon authored on 3 Sep 2019 Lionel Debieve committed on 20 Jan 2020
	e76d9fc Browse files » lib: utils_def: add CLAMP macro ... Add the standard CLAMP macro. It ensures that x is between the limits set by low and high. If low is greater than high the result is undefined. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Ia173bb9ca51bc8d9a8ec573bbc15636a94f881f4 Lionel Debieve committed on 20 Jan 2020
	162fc18 Browse files » compiler_rt: Import popcountdi2.c and popcountsi2.c files ... Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __popcountsi2(si_int a) and __popcountdi2(di_int a) builtin which are required by a driver that uses a __builtin_popcount(). Change-Id: I8e0d97cebdd90d224690c8ce1b02e657acdddb25 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
	a13550d Browse files » Add SPI-NOR framework ... SPI-NOR framework is based on SPI-MEM framework using spi_mem_op execution interface. It implements read functions and allows NOR configuration up to quad mode. Default management is 1 data line but it can be overridden by platform. It also includes specific quad mode configuration for Spansion, Micron and Macronix memories. Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Lionel Debieve committed on 20 Jan 2020
	c3e5773 Browse files » Add SPI-NAND framework ... This framework supports SPI-NAND and is based on the SPI-MEM framework for SPI operations. It uses a common high level access using the io_mtd. It is limited to the read functionalities. Default behavior is the basic one data line operation but it could be overridden by platform. Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Lionel Debieve committed on 20 Jan 2020
	05e6a56 Browse files » Add SPI-MEM framework ... This framework supports SPI operations using a common spi_mem_op structure: - command - addr - dummy - data The framework manages SPI bus configuration: - speed - bus width (Up to quad mode) - chip select Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Lionel Debieve committed on 20 Jan 2020
	b114abb Browse files » Add raw NAND framework ... The raw NAND framework supports SLC NAND devices. It introduces a new high level interface (io_mtd) that defines operations a driver can register to the NAND framework. This interface will fill in the io_mtd device specification: - device_size - erase_size that could be used by the io_storage interface. NAND core source file integrates the standard read loop that performs NAND device read operations using a skip bad block strategy. A platform buffer must be defined in case of unaligned data. This buffer must fit to the maximum device page size defined by PLATFORM_MTD_MAX_PAGE_SIZE. The raw_nand.c source file embeds the specific NAND operations to read data. The read command is a raw page read without any ECC correction. This can be overridden by a low level driver. No generic support for write or erase command or software ECC correction. NAND ONFI detection is available and can be enabled using NAND_ONFI_DETECT=1. For non-ONFI NAND management, platform can define required information. Change-Id: Id80e9864456cf47f02b74938cf25d99261da8e82 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Lionel Debieve committed on 20 Jan 2020
2020-01-17	45cc606 Browse files » Merge changes from topic "ld/mtd_framework" into integration ... * changes: io: change seek offset to signed long long compiler_rt: Import aeabi_ldivmode.S file and dependencies Soby Mathew authored on 17 Jan 2020 TrustedFirmware Code Review committed on 17 Jan 2020
	5a4b090 Browse files » Merge "zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node" into integration Mark Dykes authored on 17 Jan 2020 TrustedFirmware Code Review committed on 17 Jan 2020
	8bac368 Browse files » Merge changes from topic "add-versal-soc-support" into integration ... * changes: zynqmp: pm: clock: Move custom flags to typeflags zynqmp: pm: clock: Add support for custom type flags plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list Mark Dykes authored on 17 Jan 2020 TrustedFirmware Code Review committed on 17 Jan 2020
	992d2fe Browse files » docs: Add upcoming Change Log to Table of Contents ... Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I2a7f38eaae3a78fc3caa37833af755c15e8236ce laurenw-arm committed on 17 Jan 2020
	e74c62e Browse files » Tegra194: platform handler for entering CPU standby state ... This patch implements a handler to enter the standby state on Tegra194 platforms. On receiving a CPU_STANDBY state request, the platform handler issues TEGRA_NVG_CORE_C6 request to the MCE firmware to take the CPU into the standby state. Change-Id: I703a96ec12205853ddb3c3871b23e338e1f60687 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar authored on 27 Dec 2017 Manish Pandey committed on 17 Jan 2020