The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)

Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Extend the CCU tables with secure SRAM window in all board
setups that uses SoCs based on AP806/AP807 North Bridges

Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Change a topology map from internal database
to SPD based for 32bit bus width mode

Change-Id: I803166893ddc2fd916fc8a1c27fffd34b6ec0c72
Signed-off-by: Alex Leibovich <alexl@marvell.com>

This commit introduces 32-bit DDR topology map initialization.
For that purpose a new DDR32 build flag is added, with
according documentation update.

Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01
Signed-off-by: Alex Leibovich <alexl@marvell.com>

As a preparation for upcoming support for CN9130 platform, which is
classified as OcteonTx2 product but inherits functionality from a8k,
allow to use a8k_common.mk and mss_common.mk from outside of
PLAT_FAMILY_BASE.
Above is done by introducing BOARD_DIR which needs to be set by each
platform, before including a8k_common.mk and mss_common.mk. This will
allow to use mentioned mk files not only for platforms located under
previously defined PLAT_FAMILY_BASE.

Change-Id: I22356c99bc0419a40ae11e42f37acd50943ea134
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.

Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>