FVP: Add BL2 hash calculation in BL1 ...

This patch provides support for measured boot by adding calculation
of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB.

Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "Fix 'tautological-constant-compare' error" into integration

Fix 'tautological-constant-compare' error ...

Fixed below 'tautological-constant-compare' error when building the source
code with latest clang compiler <clang version 11.0.0>.

plat/common/plat_psci_common.c:36:2:
error: converting the result of '<<' to a boolean always evaluates
to true [-Werror,-Wtautological-constant-compare]
        PMF_STORE_ENABLE)
        ^
include/lib/pmf/pmf.h:28:29: note: expanded from macro 'PMF_STORE_ENABLE'
PMF_STORE_ENABLE        (1 << 0)

This error is observed beacuse of CASSERT placed in
"PMF_DEFINE_CAPTURE_TIMESTAMP" which do below stuff:
CASSERT(_flags, select_proper_config);
where _flags = PMF_STORE_ENABLE (1 << 0) which always results true.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifa82ea202496a23fdf1d27ea1798d1f1b583a021

Merge "spm: Add spci manifest binding document" into integration

Merge "fconf: Clean Arm IO" into integration

Merge "plat/sgi: Bump bl1 RW limit" into integration

Merge "corstone700: updating the kernel arguments to support initramfs" into integration

Merge "context: TPIDR_EL2 register not saved/restored" into integration

corstone700: updating the kernel arguments to support initramfs ...

In the context of enabling initramfs this change makes
the kernel arguments compatible with the initramfs requirements

Change-Id: Ifa955a5790ae1398fd8ad9ca1c8272f019c121a6
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

Merge "spmd: skip loading of secure partitions on pre-v8.4 platforms" into integration

spmd: skip loading of secure partitions on pre-v8.4 platforms ...

When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1
then there is no need for TF-A to load secure partitions individually.
In this configuration, SPMC handles secure partition loading at
S-EL1/EL0 levels.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I06a0d88a4811274a8c347ce57b56bb5f64e345df

Merge changes from topic "static_analysis" into integration ...

* changes:
  io: io_stm32image: correct possible NULL pointer dereference
  plat/st: correctly check pwr-regulators node
  nand: stm32_fmc2_nand: correct xor_ecc.val assigned value
  plat/st: correct static analysis tool warning
  raw_nand: correct static analysis tool warning
  spi: stm32_qspi: correct static analysis issues

io: io_stm32image: correct possible NULL pointer dereference ...

This issue was found with cppcheck in our downstream code:
[drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]:
 (warning) Either the condition 'buffer!=0U' is redundant or there is
 possible null pointer dereference: local_buffer.

Change-Id: Ieb615b7e485dc93bbeeed4cd8bf845eb84c14ac9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

plat/st: correctly check pwr-regulators node ...

This warning was issued by cppcheck in our downstream code:
[plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]:
 (warning) Identical condition 'node<0', second condition is always false

The second test has to check variable pwr_regulators_node.

Change-Id: I4a20c4a3ac0ef0639c2df36309d90a61c02b511f
Signed-off-by: Yann Gautier <yann.gautier@st.com>

nand: stm32_fmc2_nand: correct xor_ecc.val assigned value ...

The variable is wrongly set to 0L, whereas it is an unsigned int, it should
then be 0U.

Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238
Signed-off-by: Yann Gautier <yann.gautier@st.com>

plat/st: correct static analysis tool warning ...

Correct the following sparse warnings:
plat/st/common/stm32mp_dt.c:103:5: warning:
 symbol 'fdt_get_node_parent_address_cells' was not declared.
 Should it be static?
plat/st/common/stm32mp_dt.c:123:5: warning:
 symbol 'fdt_get_node_parent_size_cells' was not declared.
 Should it be static?

As those 2 functions are only used by assert(), put them under
ENABLE_ASSERTIONS flag.

Change-Id: Iad721f12128df83a3de3f53e7920a9c1dce64c56
Signed-off-by: Yann Gautier <yann.gautier@st.com>

raw_nand: correct static analysis tool warning ...

Correct the following warning given by sparse tool:
include/drivers/raw_nand.h:158:3: warning:
 symbol '__packed' was not declared. Should it be static?

Change-Id: I03bd9a8aee5cdc5212ce5225be8033f1a6e92bd9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

spi: stm32_qspi: correct static analysis issues ...

Sparse issue:
drivers/st/spi/stm32_qspi.c:445:5:
 warning: symbol 'stm32_qspi_init' was not declared. Should it be static?

Cppcheck issue:
[drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]:
 (style) Variable 'len' is reassigned a value before the old one has been
 used.
[drivers/st/spi/stm32_qspi.c:178]:
 (style) The scope of the variable 'timeout' can be reduced.

Change-Id: I575fb50766355a6717cbd193fc4a80ff1923014c
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Merge "allwinner: H6: Fix GPIO and CCU memory map addresses" into integration

Merge changes from topic "tegra-downstream-03192020" into integration ...

* changes:
  Tegra194: move cluster and CPU counter to header file.
  Tegra: gicv2: initialize target masks
  spd: tlkd: support new TLK SMCs for RPMB service
  Tegra210: trigger CPU0 hotplug power on using FC
  Tegra: memctrl: cleanup streamid override registers
  Tegra: memctrl_v2: remove support to secure TZSRAM
  Tegra: include platform headers from individual makefiles
  Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro
  Tegra194: SiP function ID to read SMMU_PER registers
  Tegra: memctrl: map video memory as uncached
  Tegra: remove support for USE_COHERENT_MEM
  Tegra: remove circular dependency with common_def.h
  Tegra: include missing stdbool.h
  Tegra: remove support for SEPARATE_CODE_AND_RODATA=0

spm: Add spci manifest binding document ...

The manifest binding document defines the expected properties and their formats
to represent a partition manifest in device tree.

Change-Id: I5eb250c7b89e0d828e1fcfce32b121e4081879ec
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Merge "plat/arm/sgi: mark remote chip shared ram as non-cacheable" into integration

Merge changes I8ca411d5,Ib5f5dd81,I0488e22c into integration ...

* changes:
  plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE
  plat: imx: imx8qm: provide debug uart num as build param
  plat: imx: imx8_iomux: fix shift-overflow errors

allwinner: H6: Fix GPIO and CCU memory map addresses ...

The base address for both the GPIO and the clock unit of the H6 memory map
have been typo-ed. Fix them to match the Linux DT and the manual.

The H6 code use neither of them, so this doesn't change or fix anything
in the real world, but should be corrected anyway.

The issue was found and reported by Github user "armlabs".

Change-Id: Ic6fdfb732ce1cfc54cbb927718035624a06a9e08
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Tegra194: move cluster and CPU counter to header file. ...

MISRA rules request that the cluster and CPU counter be unsigned
values and have a suffix 'U'. If the define located in the makefile,
this cannot be done.

This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER
macros to tegra_def.h as a result.

Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Tegra: gicv2: initialize target masks ...

This patch initializes the target masks in the GICv2 driver
data, for all PEs. This will allow platforms to set the PE
target for SPIs.

Change-Id: I7bf2ad79c04c2555ab310acba17823fb157327a3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

spd: tlkd: support new TLK SMCs for RPMB service ...

This patch adds support to handle following TLK SMCs:
{TLK_SET_BL_VERSION, TLK_LOCK_BL_INTERFACE, TLK_BL_RPMB_SERVICE}

These SMCs need to be supported in ATF in order to forward them to
TLK. Otherwise, these functionalities won't work.

Brief:
TLK_SET_BL_VERSION: This SMC is issued by the bootloader to supply its
version to TLK. TLK can use this to prevent rollback attacks.

TLK_LOCK_BL_INTERFACE: This SMC is issued by bootloader before handing off
execution to the OS. This allows preventing sensitive SMCs being used
by the OS.

TLK_BL_RPMB_SERVICE: bootloader issues this SMC to sign or verify RPMB
frames.

Tested by: Tests TLK can receive the new SMCs issued by bootloader

Change-Id: I57c2d189a5f7a77cea26c3f8921866f2a6f0f944
Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com>

Tegra210: trigger CPU0 hotplug power on using FC ...

Hotplug poweron is not working for boot CPU as it's being
triggerred using PMC and not with Flow Controller. This is
happening because "cpu_powergate_mask" is only getting set
for non-boot CPU's as the boot CPU's first bootup follows
different code path. The patch is marking a CPU as ON within
"cpu_powergate_mask" when turning its power domain on
during power on. This will ensure only first bootup on all
CPU's is using PMC and subsequent hotplug poweron will be
using Flow Controller.

Change-Id: Ie9e86e6f9a777d41508a93d2ce286f31307932c2
Signed-off-by: sumitg <sumitg@nvidia.com>

Tegra: memctrl: cleanup streamid override registers ...

Streamid override registers are passed to memctrl to program bypass
streamid for all the registers. There is no reason to bypass SMMU
for any of the client so need to remove register list and do not
set streamid_override_cfg.

Some Tegra186 platforms don't boot due to SDMMC failure so keep SDMMC
bypass as of now. Will revisit once these issues are fixed.

Change-Id: I3f67e2a0e1b53160e2218f3acace7da45532f934
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra: memctrl_v2: remove support to secure TZSRAM ...

This patch removes support to secure the on-chip TZSRAM memory for
Tegra186 and Tegra194 platforms as the previous bootloader does that
for them.

Change-Id: I50c7b7f9694285fe31135ada09baed1cfedaaf07
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>