Tegra: assembly version of the 'plat_core_pos_by_mpidr' handler ...

The 'plat_core_pos_by_mpidr' handler gets called very early during boot
and the compiler generated code overwrites the caller's registers.

This patch converts the 'plat_core_pos_by_mpidr' handler into an assembly
function and uses registers x0-x3, to fix this anomaly.

Change-Id: I8d974e007a0bad039defaf77b11a180d899ead3c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: reset power state info for CPUs ...

We set deepest power state when offlining a core but that may not be
requested by non-secure sw which controls idle states. It will re-init
this info from non-secure software when the core come online.

This patch resets the power state in the non-secure world context
to allow it to start with a clean slate.

Change-Id: Iafd92cb2a49571aa6eeb9580beaaff4ba55a87dc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: system resume from TZSRAM memory ...

TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores the contents to TZSRAM during System Resume.

This patch removes the code that sets up CPU vector to point to
TZSRAM during System Resume as a result. The trampoline code can
also be completely removed as a result.

Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: disable PROGRAMMABLE_RESET_ADDRESS ...

This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.

Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: SE: switch SE clock source to CLK_M ...

In SE suspend, switch SE clock source to CLK_M,
to make sure SE clock is on when saving SE context

Change-Id: I57c559825a3ec8e0cc35f7a389afc458a5eed0cb
Signed-off-by: Leo He <leoh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: increase platform assert logging level to VERBOSE ...

This patch increases the assert logging level for all Tegra platforms
to VERBOSE, to print the actual assertion condition to the console,
improving debuggability.

Change-Id: If3399bde63fa4261522cab984cc9c49cd2073358
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: enable dual execution for EL2 and EL3 ...

This patch enables dual execution optimized translations for EL2 and EL3
CPU exception levels.

Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: aarch64: calculate core position from one place ...

This patch updates 'plat_my_core_pos' handler to call
'plat_core_pos_from_mpidr' instead of implementing the same logic
at two places.

Change-Id: I1e56adaa10dc2fe3440e5507e0e260d8932e6657
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra194: Update t194_nvg.h to v6.7 ...

This patch updates the t194_nvg.h header file received from the CPU
team to v6.7.

Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Merge changes from topic "rpix-multi-console" into integration ...

* changes:
  rpi: docs: Update maintainers file to new RPi directory scheme
  rpi: console: Autodetect Mini-UART vs. PL011 configuration
  rpi3: build: Include GPIO driver in all BL stages
  rpi: Allow using PL011 UART for RPi3/RPi4
  rpi3: console: Use same "clock-less" setup scheme as RPi4
  rpi3: gpio: Simplify GPIO setup

Merge "Implement SMCCC_ARCH_SOC_ID SMC call" into integration

Merge "FVP: In BL31/SP_MIN, map only the needed DRAM region statically" into integration

Merge "board/rddaniel: add NSAID sources for TZC400 driver" into integration

FVP: In BL31/SP_MIN, map only the needed DRAM region statically ...

Rather than creating entry in plat_arm_mmap array to map the
entire DRAM region in BL31/SP_MIN, only map a smaller region holding
HW_CONFIG DTB. Consequently, an increase in number of sub-translation
tables(level-2 and level-3) i.e., MAX_XLAT_TABLES is necessary to map
the new region in memory.

In order to accommodate the increased code size in BL31 i.e.,
PROGBITS, the max size of BL31 image is increased by 0x1000(4K).

Change-Id: I540b8ee550588e22a3a9fb218183d2ab8061c851
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

rpi: console: Autodetect Mini-UART vs. PL011 configuration ...

The Raspberry Pi has two different UART devices pin-muxed to GPIO 14&15:
One ARM PL011 one and the 8250 compatible "Mini-UART".
A dtoverlay parameter in config.txt will tell the firmware to switch
between the two: it will setup the right clocks and will configure the
pinmuxes accordingly.

To autodetect the user's choice, we read the pinmux register and check
its setting: ALT5 (0x2) means the Mini-UART is used, ALT0 (0x4) points
to the PL011.
Based on that we select the UART driver to initialise.

This will allow console output in any case.

Change-Id: I620d3ce68de6c6576599f2a405636020e1fd1376
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

rpi3: build: Include GPIO driver in all BL stages ...

So far the Raspberry Pi 3 build needs the GPIO driver just for BL2.
Upcoming changes will require some GPIO code in BL1 and BL31 also, so
move those driver files into the common source section.

This does not affect BL31 code size at all, and bl1.bin just increases
by 144 bytes, but doesn't affect the padded binary size at all.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I7639746dc241c1e69099d85d2671c65fa0108555

rpi: Allow using PL011 UART for RPi3/RPi4 ...

The Broadcom 283x SoCs feature multiple UARTs: the mostly used
"Mini-UART", which is an 8250 compatible IP, and at least one PL011.
While the 8250 is usually used for serial console purposes, it suffers
from a design flaw, where its clock depends on the VPU clock, which can
change at runtime. This will reliably mess up the baud rate.
To avoid this problem, people might choose to use the PL011 UART for
the serial console, which is pin-mux'ed to the very same GPIO pins.
This can be done by adding "miniuart-bt" to the "dtoverlay=" line in
config.txt.

To prepare for this situation, use the newly gained freedom of sharing
one console_t pointer across different UART drivers, to introduce the
option of choosing the PL011 for the console.

This is for now hard-coded to choose the Mini-UART by default.
A follow-up patch will introduce automatic detection.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I8cf2522151e09ff4ff94a6d396aec6fc4b091a05

rpi3: console: Use same "clock-less" setup scheme as RPi4 ...

In the wake of the upcoming unification of the console setup code
between RPi3 and RPi4, extend the "clock-less" setup scheme to the
RPi3. This avoid programming any clocks or baud rate registers,
which makes the port more robust against GPU firmware changes.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ida83a963bb18a878997e9cbd55f8ceac6a2e1c1f

rpi3: gpio: Simplify GPIO setup ...

There is really no reason to use and pass around a struct when its only
member is the (fixed) base address.

Remove the struct and just use the base address on its own inside the
GPIO driver. Then set the base address automatically.

This simplifies GPIO setup for users, which now don't need to deal with
zeroing a struct and setting the base address anymore.

Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Implement SMCCC_ARCH_SOC_ID SMC call ...

Implemented SMCCC_ARCH_SOC_ID call in order to get below
SOC information:

1. SOC revision
2. SOC version

Implementation done using below SMCCC specification document:
https://developer.arm.com/docs/den0028/c

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie0595f1c345a6429a6fb4a7f05534a0ca9c9a48b

plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE ...

Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A53
doesn't make sense (since UART pinmux/clock configuration is applied
for UART only when DEBUG_CONSOLE_A53 is enabled).

Enable DEBUG_CONSOLE_A53 if DEBUG_CONSOLE is enabled.

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I8ca411d5544658b9bcc39e5340ec042c51088b96

plat: imx: imx8qm: provide debug uart num as build param ...

This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
provided via DT) to set this configuration during compile time via
IMX_DEBUG_UART build flag.

Usage:
$ make PLAT=imx8qm IMX_DEBUG_UART=1 bl31

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: Ib5f5dd81ba0c8ad2b2dc5647ec75629072f511c5

plat: imx: imx8_iomux: fix shift-overflow errors ...

This fixes shift overflow errors, when compiled with CONSOLE_DEBUG
support:

plat/imx/common/include/imx8_iomux.h:11:35: error: result of ‘1 << 31’
requires 33 bits to represent, but ‘int’ only has 32 bits
[-Werror=shift-overflow=]

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I0488e22c30314ba27caabc5c767164baa1e8004c

fconf: Clean Arm IO ...

Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This
removes the duplicate io_policies and functions definition.

This patch:
- replace arm_io_storage.c with the content of arm_fconf_io_storage.c
- rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB.
- use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb.
- propagate DEFINES when parsing dts.
- use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb.
- set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior
  of fvp stays the same as it was before the introduction of fconf.

Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Merge "SPMD: Add support for SPCI_ID_GET" into integration

plat/sgi: Bump bl1 RW limit ...

Increase bl1 RW limit to allow future development.

Change-Id: I3159b36dbaca798b4c4374c1415cd033d6586388
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Merge "juno/sgm: Maximize space allocated to SCP_BL2" into integration

SPMD: Add support for SPCI_ID_GET ...

This patch introduces the `SPCI_ID_GET` interface which will return the
ID of the calling SPCI component. Returns 0 for requests from the
non-secure world and the SPCI component ID as specified in the manifest
for secure world requests.

Change-Id: Icf81eb1d0e1d7d5c521571e04972b6e2d356e0d1
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>

Merge changes from topic "mp/enhanced_pal_hw" into integration ...

* changes:
  plat/arm/fvp: populate pwr domain descriptor dynamically
  fconf: Extract topology node properties from HW_CONFIG dtb
  fconf: necessary modifications to support fconf in BL31 & SP_MIN
  fconf: enhancements to firmware configuration framework

juno/sgm: Maximize space allocated to SCP_BL2 ...

To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its current (mostly) arbitrary address to the beginning
of the non-shared trusted SRAM.

Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434
Signed-off-by: Chris Kay <chris.kay@arm.com>