trusty: Add boot parameter documentation ...

Change-Id: Ibfb75145e3a31ae2106eedfbe4a91c2e31bb9f2a

trusty: Fix another reported misra violation ...

Change-Id: I822ccf5852dce4c01f98382cc393331f29e1e256

trusty: Fix reported misra violation ...

memset does not return a useful result here, so explitcitly ignore it

Change-Id: I33cd2228cadc280ee8e5ce3a4f8682dde9a7c16c

trusty: Fix reported static check errors ...

Change-Id: I9f9a8a159b41be1c865a20801d03a1b2934c3cac

trusty: Change type of aarch32 flag t bool ...

Change-Id: Ie4f937808d24c9b45066c6582c4eee61699ef6df

tegra/trusty: Setup tegra specific trusty args in platform code ...

Fixes tegra build with SPD=trusty. Not tested.

Change-Id: I851a2b00b8b1cc65112b6088980a811d8eda1a99

trusty: generic-arm64-smcall: Use SPDX license identifiers ...

Signed-off-by: Arve Hjønnevåg <arve@android.com>

trusty: Pass cpu suspend/resume reason to trusty ...

Add off/on argument to SMC_FC_CPU_SUSPEND SMC_FC_CPU_RESUME and pass
1 when called from the cpu on/off hooks.

Change-Id: Ie233c446fd38b3ff8546e445a8d86a15d2816093
Signed-off-by: Arve Hjønnevåg <arve@android.com>

trusty: Run bl33 in EL1 instead of EL2 is trusty image is 32-bit ...

The secure physical timer is inacessible from 32-bit S-EL1 (when EL3
is 64-bit) so trusty will use the non-secure physical timer in this
case. Linux will use the virtual timer instead of the physical timer
when started in EL1.

Change-Id: Ie49348d9a27e5287676dd4a77f678ecbd6c2309f
Signed-off-by: Arve Hjønnevåg <arve@android.com>

trusty: Add fpu/simd support ...

The original patch has been partly merged. This adds the missing
pieces.

Change-Id: I77fd434feab396ff05d9b8e0c1761e4dd588a701
Signed-off-by: Arve Hjønnevåg <arve@android.com>

trusty: Add generic-arm64 support ...

Add smc calls to return gic base address and print to the debug
console. Allows running a generic trusty binary.

Change-Id: I4b6540f140f11432cdff43c3f5a2097df09dc9d1
Signed-off-by: Arve Hjønnevåg <arve@android.com>

trusty: Restore working trusty setup code and include trusty image in build ...

Change-Id: I081901e7df22f78dd9c4fc4c6bfad2aceb870a2d
Signed-off-by: Arve Hjønnevåg <arve@android.com>

Merge pull request #1223 from vchong/poplar_bl1loadsfip ...

poplar: Enable emmc and recovery build support

Merge pull request #1193 from jwerner-chromium/JW_coreboot ...

New console API and coreboot support [v4]

Merge pull request #1233 from soby-mathew/sm/rm_uniphier_override ...

Allow API deprecation for uniphier platform

Allow API deprecation for uniphier platform ...

The `override ERROR_DEPRECATION = 1` setting in uniphier platform
makes deprecation of API difficult. Hence removing the same. This
flag should be specified on the command line if needed.

Change-Id: I8c82d8d13944e450a8cd636de3326137c04d7560
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

poplar: Add support for recovery build ...

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

poplar: Enable emmc support ...

Let bl1 and bl2 have the ability to load images from emmc instead of
dram (mmap).

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Merge pull request #1229 from manojkumar-arm/manojkumar-arm/ca72-aarch32-reset-fix ...

lib/cpus: fix branching in reset function for cortex-a72 AARCH32 mode

Merge pull request #1227 from geesun/qx/emmc_macros ...

emmc: add macros CMD21, BUS_WIDTH_DDR_4 and BUS_WIDTH_DDR_8

coreboot: Add support for CBMEM console ...

coreboot supports an in-memory console to store firmware logs even when
no serial console is available. It is widely supported by
coreboot-compatible bootloaders (including SeaBIOS and GRUB) and can be
read by the Linux kernel.

This patch allows BL31 to add its own log messages to this console. The
driver will be registered automatically if coreboot support is compiled
in and detects the presence of a console buffer in the coreboot tables.

Change-Id: I31254dfa0c2fdeb7454634134b5707b4b4154907
Signed-off-by: Julius Werner <jwerner@chromium.org>

rockchip: Move to MULTI_CONSOLE_API ...

This patch changes all Rockchip platforms to use the new
MULTI_CONSOLE_API. The platform-specific plat_crash_console
implementations are removed so that the platform can use the ones from
the common platform code instead.

Also change the registers used in plat_crash_print_regs. The existing
use of x16 and x17 has always been illegal, since those registers are
reserved for use by the linker as a temporary scratch registers in
intra-procedure-call veneers and can never be expected to maintain their
values across a function call.

Change-Id: I8249424150be8d5543ed4af93b56756795a5288f
Signed-off-by: Julius Werner <jwerner@chromium.org>

rockchip: Use coreboot-supplied serial console on coreboot systems ...

This patch changes all Rockchip platforms to initialize the serial
console with information supplied by coreboot rather than hardcoded
base address and divisor values if BL31 is run on top of coreboot.
Moving the BL2-to-BL31 parameter parsing as early as possible to ensure
that the console is available for all following code.

Also update the Rockchip platform to use MULTI_CONSOLE_API.

Change-Id: I670d350fa2f8b8133539f91ac14977ab47db60d9
Signed-off-by: Julius Werner <jwerner@chromium.org>

Add platform-independent coreboot support library ...

This patch adds the foundation for a platform-independent coreboot
support library that can be shared by all platforms that boot BL31 from
coreboot (acting as BL2). It adds code to parse the "coreboot table", a
data structure that coreboot uses to communicate different kinds of
information to later-stage firmware and certain OS drivers.

As a first small use case for this information, allow platforms to
access the serial console configuration used by coreboot, removing the
need to hardcode base address and divisors and allowing Trusted Firmware
to benefit from coreboot's user configuration (e.g. which UART to pick
and which baud rate to use).

Change-Id: I2bfb39cd2609ce6640b844ab68df6c9ae3f28e9e
Signed-off-by: Julius Werner <jwerner@chromium.org>

drivers: cadence: cdns: Update CDNS driver to support MULTI_CONSOLE_API ...

This patch updates the Cadence CDNS console driver to support the new
console API. The driver will continue to support the old API as well by
checking the MULTI_CONSOLE_API compile-time flag.

Change-Id: I2ef8fb0d6ab72696997db1e0243a533499569d6b
Signed-off-by: Julius Werner <jwerner@chromium.org>

drivers: arm: pl011: Update PL011 driver to support MULTI_CONSOLE_API ...

This patch updates the ARM PL011 console driver to support the new
console API. The driver will continue to support the old API as well by
checking the MULTI_CONSOLE_API compile-time flag.

Change-Id: Ic34e4158addbb0c5fae500c9cff899c05a4f4206
Signed-off-by: Julius Werner <jwerner@chromium.org>

drivers: ti: uart: Update 16550 UART driver to support MULTI_CONSOLE_API ...

This patch updates the TI 16550 console driver to support the new
console API. The driver will continue to support the old API as well by
checking the MULTI_CONSOLE_API compile-time flag.

Change-Id: I60a44b7ba3c35c74561824c04b8dbe3e3039324c
Signed-off-by: Julius Werner <jwerner@chromium.org>

Add default crash console code to hook up to new console API ...

This patch expands the weak stubs for the plat_crash_console_xxx
functions in common platform code to use the new console API for crash
output. This should make crash console output "just work" for most cases
without the need for the platform to explicitly set up a crash console.
For cases where the normal console framework doesn't work (e.g. very
early crashes, before the platform can register any consoles), platforms
are still able to override the functions just like before.

This feature requires the MULTI_CONSOLE_API compile-time flag to work.
For builds which don't have it set, this patch has no practical effect.

Change-Id: I80dd161cb43f9db59a0bad2dae33c6560cfac584
Signed-off-by: Julius Werner <jwerner@chromium.org>

Merge pull request #1200 from robertovargas-arm/bl2-el3 ...

Add BL2_AT_EL3 build option

lib/cpus: fix branching in reset function for cortex-a72 AARCH32 mode ...

In AARCH32 mode, cortex_a72_reset_func branches to address in lr
register instead of r5 register. This leads to linux boot failure
of Cortex-A72 cores in AARCH32 mode on Juno-R2 board.

This patch fixes the branching of cortex_a72_reset_func to r5
register as in cortex_a57_reset_func implementation.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>