Merge "Introduce BTI support in ROMLIB" into integration

mediatek: mt8183: add mcsi driver ...

add mcsi driver to support cache coherence.

Change-Id: I94f5922783e5dbc6b7e92aa06464bc1f0177f00a
Signed-off-by: kenny liang <kenny.liang@mediatek.com>

mediatek: mt8183: add GIC driver ...

Add Mediatek GIC driver to support interrupt functions.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I967a18f2e45b7bbc88c506dd4f1f40a745227ad9

Merge "Apply compile-time check for AArch64-only cores" into integration

Merge "Prevent pending G1S interrupt become G0 interrupt" into integration

Prevent pending G1S interrupt become G0 interrupt ...

According to Arm GIC spec(IHI0069E, section 4.6.1),
when GICD_CTLR.DS == 0, Secure Group 1 interrupts
are treated as Group 0 by a CPU interface if:
- The PE does not implement EL3.
- ICC_SRE_EL1(S).SRE == 0

When a cpu enter suspend or deep idle, it might be
powered off. When the cpu resume, according to
the GIC spec(IHI0069E, section 9.2.15, 9.2.16 and
9.2.22) the ICC_SRE_EL1.SRE reset value is 0 (if
write is allowed) and G0/G1S/G1NS interrupt of the
GIC cpu interface are all disabled.

If a G1S SPI interrupt occurred and the target cpu
of the SPI is assigned to a specific cpu which is
in suspend and is powered off, when the cpu resume
and start to initial the GIC cpu interface, the
initial sequence might affect the interrupt group
type of the pending interrupt on the cpu interface.

Current initial sequence on the cpu interface is:
1. Enable G0 interrupt
2. Enable G1S interrupt
3. Enable ICC_SRE_EL1(S).SRE

It is possible to treat the pending G1S interrupt
as G0 interrupt on the cpu interface if the G1S
SPI interrupt occurred between step2 and step3.

To prevent the above situation happend, the initial
sequence should be changed as follows:
1. Enable ICC_SRE_EL1(S).SRE
2. Enable G0 interrupt
3. Enable G1S interrupt

Change-Id: Ie34f6e0b32eb9a1677ff72571fd4bfdb5cae25b0
Signed-off-by: James Kung <kong1191@gmail.com>

Apply compile-time check for AArch64-only cores ...

Some cores support only AArch64 mode. In those cores, only a limited
subset of the AArch32 system registers are implemented. Hence, if TF-A
is supposed to run on AArch64-only cores, it must be compiled with
CTX_INCLUDE_AARCH32_REGS=0.

Currently, the default settings for compiling TF-A are with the AArch32
system registers included. So, if we compile TF-A the default way and
attempt to run it on an AArch64-only core, we only get a runtime panic.

Now a compile-time check has been added to ensure that this flag has the
appropriate value when AArch64-only cores are included in the build.

Change-Id: I298ec550037fafc9347baafb056926d149197d4c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge "doc: Enable automatic labels for page titles" into integration

Merge "Add information about the mailing list in the docs" into integration

Add information about the mailing list in the docs ...

Change-Id: I41ce5323c33a81db13c5cc40de1ac4e221a10cd8
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge changes from topic "jts/docs" into integration ...

* changes:
  Removing IRC related info from the documentation
  Further fixes to documentation links

Removing IRC related info from the documentation ...

Change-Id: I5cf8c70a304bf5869cbeb12fa8d39171cff48ebd
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge "rockchip: drop rockchip-specific imported linker symbols for bl31" into integration

doc: Enable automatic labels for page titles ...

Automatic labelling of document titles is a prerequisite for
converting the format of cross-document links. Sphinx will
generate (via the enabled extension) a hidden link target for
each document title and this can be referred to later, from
another page, to link to the target.

The plugin options being used require Sphinx >= 2.0.0 so a
requirements.txt file has been added. This file is used with
the pip package manager for Python so that the correct
dependencies are installed.

Change-Id: Ic2049db5804aa4a6447608ba4299de958ce0a87d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Further fixes to documentation links ...

Change-Id: Ib021c721652d96f6c06ea18741f19a72bba1d00f
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge "Cortex-A55: workarounds for errata 1221012" into integration

rockchip: drop rockchip-specific imported linker symbols for bl31 ...

In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are
currently imported into special BL31_RO_* constants while the general
code also imports them as BL_CODE_BASE and BL_CODE_END.

So we can just use the general symbols and can drop the duplication.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ibf1b48ad80bed897247a1690a32711030479262d

Merge "Beautify "make help"" into integration

Merge "Makefile: Add default warning flags" into integration

Cortex-A55: workarounds for errata 1221012 ...

The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.

Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Merge "plat: imx8m: Add the aipstz init to config peripheral access" into integration

Merge changes from topic "for-upstream" into integration ...

* changes:
  ti: k3: common: Set L2 latency on A72 cores
  ti: k3: common: Add support for J721E

Merge "Fix documentation links" into integration

Fix documentation links ...

Change-Id: Ic09e74f22b43fba51ee17cd02b5e1dc5d8e0bb63
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge "Add support for Branch Target Identification" into integration

Merge changes from topic "jts/docs" into integration ...

* changes:
  Docs fixes
  Update security documentation

Add support for Branch Target Identification ...

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by adding BTI instruction used to mark valid targets
for indirect branches. The patch sets new GP bit [50] to the stage 1
Translation Table Block and Page entries to denote guarded EL3 code
pages which will cause processor to trap instructions in protected
pages trying to perform an indirect branch to any instruction other
than BTI.
BTI feature is selected by BRANCH_PROTECTION option which supersedes
the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
and is disabled by default. Enabling BTI requires compiler support
and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
The assembly macros and helpers are modified to accommodate the BTI
instruction.
This is an experimental feature.
Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
is now made as an internal flag and BRANCH_PROTECTION flag should be
used instead to enable Pointer Authentication.
Note. USE_LIBROM=1 option is currently not supported.

Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Makefile: Add default warning flags ...

The flags are taken from the different warning levels of the build
system when they do not generate any error with the current upstreamed
platforms.

Change-Id: Ia70cff83bedefb6d2f0dd266394ef77fe47e7f65
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Docs fixes ...

1) Fix links in "about" page
2) Put back the "contents" page with adjusted links

Change-Id: Id09140b91df5cf0a275149801d05d8cfeeda1c6e
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Update security documentation ...

1) Replace references to "Arm Trusted Firmware" with "TF-A"
2) Update issue tracker link

Change-Id: I12d827d49f6cc34e46936d7f7ccf44e32b26a0bd
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>