synquacer: Add platform makefile and documentation ...

Add Makefile and plaform definations file.
My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces
I've taken from their earlier work regarding build and deploy steps for
Developerbox based on Synquacer SoCs. They deserve much of the credit
for this work although, since I assembled and tested things, any blame
is probably mine.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

synquacer: Enable PSCI framework ...

PSCI framework uses SCPI driver to communicate to SCP firmware for
various power management operations. Following PSCI operations are
supported:
- CPU ON
- CPU OFF
- CPU STANDBY
- SYSTEM RESET
- SYSTEM OFF

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Retrieve DRAM info from SCP firmware ...

Retrieve DRAM info from SCP firmware using SCPI driver. Board supports
multiple DRAM slots so its required to fetch DRAM info from SCP firmware
and pass this info to UEFI via non-secure SRAM.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Add SCPI driver ...

Add System Control and Power Interface (SCPI) driver which provides APIs
for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate
with SCP firmware for various system control and power operations.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Add MHU driver ...

Add Message Handling Unit (MHU) driver used to communicate among
Application Processors (AP) and System Control Processor (SCP).

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Enable MMU using xlat_tables_v2 library ...

BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Enable System level Generic timer ...

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Enable GICv3 support ...

synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver
initialization.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Enable CCN driver support ...

synquacer has CCN-512 interconnect. So enable proper CCN driver
initialization.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Implement topology functions ...

These functions describe the layout of the cores and clusters in order
to support the PSCI framework.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Populate BL32 and BL33 entrypoints ...

As this platform supports direct entry to BL31 and no BL2, so
populate BL32 and BL33 entrypoints with static memory load info.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Enable PL011 UART Console ...

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Add platform core management helpers ...

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Introduce basic platform support ...

synquacer supports direct entry to BL31 without BL1 and BL2 as
SCP firmware does similar work. So this patch adds BL31 stub APIs.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

Merge pull request #1403 from glneo/for-upstream-k3 ...

TI K3 platform support

Merge pull request #1421 from Yann-lms/cpp_dtc ...

Build: add cpp build processing for dtb

Merge pull request #1413 from grandpaul/paulliu-rpi3-0 ...

rpi3: BL32 optee support

Merge pull request #1423 from chandnich/sgi-575/dyncfg ...

Sgi 575/dyncfg

ti: k3: Introduce basic generic board support ...

While it would be useful to have a device tree based build, the
required components are not in place yet, so support just a simple
statically defined configuration to begin with.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Add PSCI stubs ...

These functions are used for the PSCI implementation and are needed to
build BL31, but we cannot implement them until we add several more drivers
related to ti-sci so these are only stubs for now.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Enable GICv3 support ...

Do proper initialization of GIC V3. This will allow CP15 access to GIC
from "normal world" (aka HLOS) via mrc/mcr calls.

K3 SoC family uses GICv3 compliant GIC500 without compatibility for
legacy GICv2.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Program A53 arch timer frequency ...

Provide K3_TIMER_FREQUENCY for the platform configuration if the GTC
clock is selected statically and override option if the platform has a
different configuration.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>

ti: k3: common: Add console initialization base ...

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Enable MMU using xlat_tables_v2 library ...

This library will be used to properly set up mappings from different
bootloaders at different exception levels. It ensures that memory mapped
devices such as UARTs are still accessible and memory regions have the
correct access permissions.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Implement topology functions ...

These functions describe the layout of the cores and clusters in order to
support the PSCI framework.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Populate BL32 and BL33 entrypoint ...

Because there is no BL2, BL31 must determine the entrypoint and memory
location of BL32 and BL33 on its own.

BL32_BASE and PRELOADED_BL33_BASE will be set in the corresponding board
makefile. We also allow a DTB address to be specified for cases when BL33
is a Linux image.

NOTE: It is possible to pull in this information from device tree as
well, however libfdt does not contain the required hooks to make this
happen at this point in time.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Add platform core management helpers ...

The K3 family of SoCs has multiple interconnects. The key interconnect
for high performance processors is the MSMC3 interconnect. This is
an io-coherent interconnect which exports multiple ports for each
processor cluster.

Sometimes, port 0 of the MSMC may not have an ARM cluster OR is isolated
such that the instance of ATF does not manage it. Define macros
in platform_def.h to help handle this.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: Setup initial files for platform ...

Create the baseline Makefile, platform definitions file and platform
specific assembly macros file. This includes first set of constants
for the platform including cache sizes and linker format and a stub for
BL31 and the basic memory layout

K3 SoC family of processors do not use require a BL1 or BL2 binary,
since such functions are provided by an system controller on the SoC.
This lowers the burden of ATF to purely managing the local ARM cores
themselves.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

Merge pull request #1410 from Anson-Huang/master ...

Add NXP's i.MX8QX and i.MX8QM SoC support

Merge pull request #1425 from jts-arm/panic ...

Panic in BL1 when TB_FW_CONFIG is invalid