ti: k3: Setup initial files for platform ...

Create the baseline Makefile, platform definitions file and platform
specific assembly macros file. This includes first set of constants
for the platform including cache sizes and linker format and a stub for
BL31 and the basic memory layout

K3 SoC family of processors do not use require a BL1 or BL2 binary,
since such functions are provided by an system controller on the SoC.
This lowers the burden of ATF to purely managing the local ARM cores
themselves.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

Merge pull request #1410 from Anson-Huang/master ...

Add NXP's i.MX8QX and i.MX8QM SoC support

Merge pull request #1425 from jts-arm/panic ...

Panic in BL1 when TB_FW_CONFIG is invalid

Merge pull request #1430 from dp-arm/dp/cpulib ...

cpulib: Add ISBs or comment why they are unneeded

Merge pull request #1418 from antonio-nino-diaz-arm/an/arm-multi-console ...

plat/arm: Migrate AArch64 port to the multi console driver

Merge pull request #1420 from Yann-lms/mm_cursor_size_check ...

xlat_v2: add a check on mm_cursor->size to avoid infinite loop

cpulib: Add ISBs or comment why they are unneeded ...

Change-Id: I18a41bb9fedda635c3c002a7f112578808410ef6
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

plat/arm: Migrate AArch64 port to the multi console driver ...

The old API is deprecated and will eventually be removed.

Arm platforms now use the multi console driver for boot and runtime
consoles. However, the crash console uses the direct console API because
it doesn't need any memory access to work. This makes it more robust
during crashes.

The AArch32 port of the Trusted Firmware doesn't support this new API
yet, so it is only enabled in AArch64 builds. Because of this, the
common code must maintain compatibility with both systems. SP_MIN
doesn't have to be updated because it's only used in AArch32 builds.
The TSP is only used in AArch64, so it only needs to support the new
API without keeping support for the old one.

Special care must be taken because of PSCI_SYSTEM_SUSPEND. In Juno, this
causes the UARTs to reset (except for the one used by the TSP). This
means that they must be unregistered when suspending and re-registered
when resuming. This wasn't a problem with the old driver because it just
restarted the UART, and there were no problems associated with
registering and unregistering consoles.

The size reserved for BL2 has been increased.

Change-Id: Icefd117dd1eb9c498921181a21318c2d2435c441
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1400 from Andre-ARM/allwinner/v1 ...

Allwinner platform support

Support for NXP's i.MX8QM SoC ...

NXP's i.MX8QM is an ARMv8 SoC with 2 clusters, 2 Cortex-A72
cores in one cluster and 4 Cortex-A53 in the other cluster,
and also has system controller (Cortex-M4) inside, documentation
can be found in below link:

https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES

This patch adds support for booting up SMP linux kernel (v4.9).

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Support for NXP's i.MX8QX SoC ...

NXP's i.MX8QX is an ARMv8 SoC with 4 Cortex-A35 cores and
system controller (Cortex-M4) inside, documentation can
be found in below link:

https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES

This patch adds support for booting up SMP linux kernel (v4.9).

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Support for NXP's imx SoC common function ...

This patch adds support for NXP's imx SoC common
function support like topology, gic implementation.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Support for NXP's imx SoC debug uart ...

Add NXP's imx SoC debug uart driver.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Support for NXP's i.MX8 SoCs IPC ...

NXP's i.MX8 SoCs have system controller (M4 core)
which takes control of clock management, power management,
partition management, PAD management etc., other
clusters like Cortex-A35 can send out command via MU
(Message Unit) to system controller for clock/power
management etc..

This patch adds basic IPC(inter-processor communication) support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Merge pull request #1426 from antonio-nino-diaz-arm/an/spm-sync ...

SPM: Refactor entry and exit of the SP

Merge pull request #1422 from Yann-lms/genmask ...

Genmask

SPM: Refactor entry and exit of the SP ...

Only use synchronous calls to enter the Secure Partition in order to
simplify the SMC handling code.

Change-Id: Ia501a045585ee0836b9151141ad3bd11d0971be2
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Panic in BL1 when TB_FW_CONFIG is invalid ...

In Arm platforms, when using dynamic configuration, the necessary
parameters are made available as a DTB. The DTB is loaded by BL1 and,
later on, is parsed by BL1, BL2 or even both, depending on when
information from the DTB is needed.

When the DTB is going to be parsed, it must be validated first, to
ensure that it is properly structured. If an invalid DTB is detected
then:
  - BL1 prints a diagnostic but allows execution to continue,
  - BL2 prints a diagnostic and panics.

Now the behaviour of BL1 is changed so for it also to panic. Thus, the
behaviour of BL1 and BL2 is now similar.

Keep in mind that if BL1 only loads the DTB but it doesn't need to
read/write it, then it doesn't validate it. The validation is done only
when the DTB is actually going to be accessed.

Change-Id: Idcae6092e6dbeab7248dd5e041d6cbb7784fe410
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

allwinner: Add security setup ...

Some peripherals are TrustZone aware, so they need to be configured to
be accessible from non-secure world, as we don't need any of them being
exclusive to the secure world.
This affects some clocks, DMA channels and the Secure Peripheral
Controller (SPC). The latter controls access to most devices, but is not
active unless booting with the secure boot fuse burnt.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

allwinner: Add platform PSCI functions required for SMP ...

The reset vector entry point is preserved across CPU resets, so it only
needs to be set once at boot.

Hotplugged CPUs are not actually powered down, but are put in a wfi with
the GIC disconnected.

With this commit, Linux is able to enable, hotplug and use all four CPUs.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

allwinner: Add functions to control CPU power/reset ...

sun50i_cpu_on will be used by the PSCI implementation to initialize
secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by
PSCI directly, because it is not possible for a CPU to use this function
to power itself down. Power cannot be shut off until the outputs are
clamped, and MMIO does not work once the outputs are clamped.

But at least CPU0 can shutdown the other cores early in the BL31 boot
process and before shutting down the system.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

allwinner: Add Allwinner A64 support ...

The Allwinner A64 SoC is quite popular on single board computers.
It comes with four Cortex-A53 cores in a singe cluster and the usual
peripherals for set-top box/tablet SoC.

The ATF platform target is called "sun50i_a64".

[Andre: adapted to amended directory layout, removed unneeded definitions ]

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

allwinner: Introduce basic platform support ...

This platform supports Allwinner's SoCs with ARMv8 cores. So far they
all sport a single cluster of Cortex-A53 cores.

"sunxi" is the original code name used for this platform, and since it
appears in the Linux kernel and in U-Boot as well, we use it here as a
short file name prefix and for identifiers.

This port includes BL31 support only. U-Boot's SPL takes the role of the
primary loader, also doing the DRAM initialization. It then loads the
rest of the firmware, namely ATF and U-Boot (BL33), then hands execution
over to ATF.

This commit includes the basic platform code shared across all SoCs.
There is no platform.mk yet.

[Andre: moved files into proper directories, supported RESET_TO_BL31,
	various clean ups and simplifications ]

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

utils: Add BIT_32 and BIT_64 macros ...

When applying some MISRA rules, lots of issues are raised with BIT macro
on AARCH32, and cast on uint32_t would be required (Rule 10.3).
The macros BIT_32 and BIT_64 are then created for 32bit and 64bit.
Then the BIT macro defaults on BIT_64 on AARCH64,
and on BIT_32 on AARCH32.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

Add GENMASK macros ...

Import GENMASK_32 and GENMASK_64 macros from optee-os (permissive license).
And default GENMASK is set to GENMASK_32 for AARCH32,
and to GENMASK_64 for 64bit arch.

fixes arm-software/tf-issues#596

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Merge pull request #1414 from antonio-nino-diaz-arm/an/fix-rpi3-doc ...

rpi3: Fix kernel boot documentation

Merge pull request #1419 from danielboulby-arm/db/docs ...

Correct ordering of log levels in documentation

Merge pull request #1417 from paulkocialkowski/integration ...

rockchip: Move stdint header to the offending header file

Merge pull request #1415 from antonio-nino-diaz-arm/an/spm-fixes ...

Minor fixes to SPM

Merge pull request #1412 from masahir0y/uniphier ...

uniphier: fix CCI-500 connection for LD20