xlat v2: Support the EL2 translation regime ...

The translation library is useful elsewhere. Even though this repository
doesn't exercise the EL2 support of the library, it is better to have it
here as well to make it easier to maintain.

enable_mmu_secure() and enable_mmu_direct() have been deprecated. The
functions are still present, but they are behind ERROR_DEPRECATED and
they call the new functions enable_mmu_svc_mon() and
enable_mmu_direct_svc_mon().

Change-Id: I13ad10cd048d9cc2d55e0fff9a5133671b67dcba
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1505 from Yann-lms/mmc_delays ...

mmc: add required delays when retrying commands

Merge pull request #1513 from antonio-nino-diaz-arm/an/xlat-caches ...

xlat v2: Cleanup and dcache coherency bug fix

xlat v2: Flush xlat tables after being modified ...

During cold boot, the initial translation tables are created with data
caches disabled, so all modifications go to memory directly. After the
MMU is enabled and data cache is enabled, any modification to the tables
goes to data cache, and eventually may get flushed to memory.

If CPU0 modifies the tables while CPU1 is off, CPU0 will have the
modified tables in its data cache. When CPU1 is powered on, the MMU is
enabled, then it enables coherency, and then it enables the data cache.
Until this is done, CPU1 isn't in coherency, and the translation tables
it sees can be outdated if CPU0 still has some modified entries in its
data cache.

This can be a problem in some cases. For example, the warm boot code
uses only the tables mapped during cold boot, which don't normally
change. However, if they are modified (and a RO page is made RW, or a XN
page is made executable) the CPU will see the old attributes and crash
when it tries to access it.

This doesn't happen in systems with HW_ASSISTED_COHERENCY or
WARMBOOT_ENABLE_DCACHE_EARLY. In these systems, the data cache is
enabled at the same time as the MMU. As soon as this happens, the CPU is
in coherency.

There was an attempt of a fix in psci_helpers.S, but it didn't solve the
problem. That code has been deleted. The code was introduced in commit
<264410306381> ("Invalidate TLB entries during warm boot").

Now, during a map or unmap operation, the memory associated to each
modified table is flushed. Traversing a table will also flush it's
memory, as there is no way to tell in the current implementation if the
table that has been traversed has also been modified.

Change-Id: I4b520bca27502f1018878061bc5fb82af740bb92
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1501 from robertovargas-arm/cci ...

cci: Wait before reading status register

Merge pull request #1512 from npoushin/integration ...

Add support for Arm System Guidance for Mobile fixed virtual platform

xlat v2: Cleanup get/change mem attr helpers ...

Changed the names for consistency with the rest of the library. Introduced
new helpers that manipulate the active translation tables context.

Change-Id: Icaca56b67fcf6a96e88aa3c7e47411162e8e6856
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

plat/arm: Add support for SGM775 ...

Add support for System Guidance for Mobile platform SGM775

Change-Id: I2442a50caae8f597e5e5949cd48f695cf75d9653
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>

css_pm_scmi: optimise cpu suspend to remove redundant scmi call ...

In css platforms where the cpu/cluster management is done by the hardware,
software does need to issue certain scmi requests.

This patch wraps those scmi calls around the HW_ASSISTED_COHERENCY
build option to remove them on platforms that have this hardware support.

Change-Id: Ie818e234484ef18549aa7f977aef5c3f0fc26c27
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>

plat/arm: tzc_dmc500: Add missing plat_arm.h include ...

This omission causes a build error as the definition for
arm_tzc_regions_info_t is needed from plat_arm.h

Change-Id: I26935ee90d3e36ab6a016ff2c4eee4413df3e4e8
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>

plat/arm: css: Set MT bit in incoming mpidr arugments ...

Change-Id: I278d6876508800abff7aa2480910306a24de5378
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>

Merge pull request #1511 from chandnich/sgi575-updates ...

Sgi575 updates

plat/sgi: switch to using scmi ...

The Arm SGI platforms can switch to using SCMI. So enable support for
SCMI and remove portions of code that would be unused after switching
to SCMI.

Change-Id: Ifd9e1c944745f703da5f970b5daf1be2b07ed14e
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

sgi: disable CPU power down bit in reset handler ...

On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1'
register requires an explicit write to clear it for hotplug and
idle to function correctly. The reset value of this bit is zero
but it still requires this explicit clear to zero. This indicates
that this could be a model related issue but for now this issue can
be fixed be clearing the CORE_PWRDN_EN in the platform specific
reset handler function.

Change-Id: I4222930daa9a3abacdace6b7c3f4a5472ac0cb19
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Merge pull request #1506 from danielboulby-arm/db/SeparateCodeAndROData ...

Fix build for SEPARATE_CODE_AND_RODATA=0

Merge pull request #1509 from antonio-nino-diaz-arm/an/bool ...

xlat: psci: Use bool instead of int

Merge pull request #1503 from ARM-software/dh/dual-lic ...

Update license information in readme.rst

Merge pull request #1508 from sandrine-bailleux-arm/sb/fix-trusty-build ...

Fix handler prototype in Trusty generic dispatcher

psci: Use bool in internal interfaces ...

Change-Id: I77c9cd2d1d6d0122cc49917fa686014bee154589
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

xlat: Use bool instead of int ...

Change-Id: I35d5b6a7c219f6f38983b30f157c1ed3808af17f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

mmc: add required delays when retrying commands ...

A new function mmc_reset_to_idle is also created.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

Merge pull request #1507 from jeenu-arm/bool ...

Define bool type

Fix build for SEPARATE_CODE_AND_RODATA=0 ...

TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never defined for
this case. Create memory region combining code and RO data for
when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this

Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

Define bool type ...

This would enable us to write semantically sensible code.

Change-Id: Ie7c75f9c024f671a037448f5c0922174fff3f0ce
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Fix handler prototype in Trusty generic dispatcher ...

Fix the types of the arguments of trusty_generic_platform_smc()
to match the expected prototype of a runtime service handler
(see rt_svc_handle_t type).

Change-Id: Ie839d116ca924b4b018ea2abbef72a1073da2a32
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge pull request #1500 from danielboulby-arm/db/RORedirection ...

Set console function pointers to const

Update license information in readme.rst ...

Added information on how disjunctively dual licensed code from
other projects is treated in the TF-A project.

Change-Id: Idca329abba4d36bd3c4fd722ac1556940b9135a2
Signed-off-by: Dan Handley <dan.handley@arm.com>

Merge pull request #1498 from glneo/cache-early-fixes ...

Early cache enable and coherency fixes

Merge pull request #1493 from antonio-nino-diaz-arm/an/xlat-misra ...

Fix MISRA defects in xlat tables lib and SP805 driver

Set console function pointers to const ...

Set the function pointers in the console struct and the functions
they point to to const since they only need to be defined when
the console is being initialised and should not be changed after

Change-Id: I0574307111e3ab2f13d1a4a74c3fa75532dfa4be
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>