| 2019-03-12 |
intel: QSPI boot enablement
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Manages QSPI initialization, configuration and IO handling as boot device
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Muhammad Hadi Asyrafi Abdul Halim
committed
on 12 Mar 2019
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plat: imx8m: Add the basic support for imx8mm
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The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-art media-specific
features with high-performance processing while optimized
for lowest power consumption. The i.MX 8M Mini Media Applications
Processor is 14nm FinFET product of the growing i.MX8M family
targeting the consumer & industrial market. It is built in 14LPP
to achieve both high performance and low power consumption
and relies on a powerful fully coherent core complex based on
a quad Cortex-A53 cluster with video and graphics accelerators
this patch add the basic support for i.MX8MM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Jacky Bai
committed
on 12 Mar 2019
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intel: Add driver for QSPI
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To support the enablement of QSPI booting
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Muhammad Hadi Asyrafi Abdul Halim
committed
on 12 Mar 2019
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plat/arm: mhu: make mhu driver generic
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MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic MHU doorbell driver.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Masahisa Kojima
committed
on 12 Mar 2019
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plat/synquacer: enable SCMI support
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Enable the SCMI protocol support in SynQuacer platform.
Aside from power domain, system power and apcore management protocol,
this commit adds the vendor specific protocol(0x80).
This vendor specific protocol is used to get the dram mapping information
from SCP.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Masahisa Kojima
committed
on 12 Mar 2019
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Allow setting compiler's target architecture
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Change-Id: I56ea088f415bdb9077c385bd3450ff4b2cfa2eac
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Alexei Fedorov
committed
on 12 Mar 2019
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Makefile: fix linking with pie and binutils > 2.27
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Since binutils 1a9ccd70f9a7[1] TFA will not link when the PIE option is
used:
aarch64-linux-gnu-ld: build/fvp/debug/bl31/bl31.elf: Not enough room
for program headers, try linking with -N
aarch64-linux-gnu-ld: final link failed: Bad value
This issue was also encountered by u-boot[2] and linux powerpc kernel
[3]. The fix is to provide --no-dynamic-linker for the linker. This
tells the linker that PIE does not need loaded program program headers.
Fix https://github.com/ARM-software/tf-issues/issues/675
[1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=1a9ccd70f9a7
[2] http://git.denx.de/?p=u-boot.git;a=commit;h=e391b1e
[3] https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?h=next&id=ff45000
Change-Id: Ic3c33c795a9b7bdeab0e87c4345153ce2703a524
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 12 Mar 2019
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PIE: Correct minor typographical errors
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Change-Id: Ie7832b2ebffe15d53ffe3584e4d23a449d4f81ac
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 12 Mar 2019
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doc: Minor formatting enhancement
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The security advisories would all appear on a single line. Use bullet
points instead to improve the readability.
Change-Id: Id631985d7d559b3632f43d695cffa6735520b64a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux
committed
on 12 Mar 2019
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doc: Fix a broken link in the readme.rst file
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Change-Id: I53a4649b17614f711957424ddffed1dcccfc7880
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux
committed
on 12 Mar 2019
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drivers: Remove TODO from io_fip.c
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The comment suggests checking version numbers and
a checksum but there doesn't seem to be any usable
data for either of these.
For example, fip_toc_header_t doesn't contain any
version information and neither does fip_toc_entry_t.
As the function name "is_valid_header" suggests, this
function is not concerned with checksumming any of
the table of contents entries.
Change-Id: I8673ae5dd37793771760169f26b2f55c15fbf587
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 12 Mar 2019
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drivers: Remove TODO from io_storage
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This TODO was added five years ago so I assume that there is not
going to be a shutdown API added after all.
Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 12 Mar 2019
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tools: Remove TODO from fiptool
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It is quite unlikely that this number will ever change and, if it
does need to change, we should have a good reason to do so. It
seems that this comment is now redundant.
Change-Id: I409c764080748e338e9bc5606bbdcc475213fb6e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 12 Mar 2019
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tools: Remove unused cert_create defines
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Change-Id: Iea72ef9ba16325cbce07eea1a975d2a96eede274
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 12 Mar 2019
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plat: imx8m: refactor the code to make it reusable
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for the i.MX8M SOCs, part of the code for gpc
and PSCI implementation can be reused and make it
common for all these SoCs. this patch extracts
the common part for reuse.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Jacky Bai
committed
on 12 Mar 2019
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Apply stricter speculative load restriction
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The SCTLR.DSSBS bit is zero by default thus disabling speculative loads.
However, we also explicitly set it to zero for BL2 and TSP images when
each image initialises its context. This is done to ensure that the
image environment is initialised in a safe state, regardless of the
reset value of the bit.
Change-Id: If25a8396641edb640f7f298b8d3309d5cba3cd79
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis
committed
on 12 Mar 2019
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drivers: synopsys: Fix synopsys MMC driver
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There are some issues with synopsys MMC driver:
- CMD8 should not expect data (for SD)
- ACMD51 should expect data (Send SCR for SD)
- dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is
now handled in the dw_prepare function
- after the CMD completes, when doing dw_read, we need to invalidate cache
and wait for the data transfer to complete
- Need to set FIFO threshold, otherwise DMA might never get the interrupt
to read or write
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Tien Hock, Loh
committed
on 12 Mar 2019
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| 2019-03-11 |
Merge pull request #1872 from Yann-lms/ocr_voltage
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mmc: stm32_sdmmc2: fill ocr_voltage
Dimitris Papastamos
authored
on 11 Mar 2019
GitHub
committed
on 11 Mar 2019
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Remove some warnings when using checkpatch with --strict option
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Some checks are ignored as they do not match TF-A coding rules:
PREFER_KERNEL_TYPES, USLEEP_RANGE
or MISRA:
COMPARISON_TO_NULL, UNNECESSARY_PARENTHESES
Change-Id: I335ede89fc872a6169028552d1ba9312fc61a0ba
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 11 Mar 2019
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Add the possibility to pass options for checkpatch
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It can be handy for example to add --strict option which can detect more
coding issues, even if not mandated by TF-A coding rules.
To use it:
CHECKPATCH_OPTS="--strict" make checkpatch
Change-Id: I707e4cc2d1250b21f18ff16169b5f1e5ab03a7ed
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 11 Mar 2019
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.checkpatch.conf: ignore BRACES warnings
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MISRA C:2012 Rule 15.6 asks to have braces for the body of an if,
for, or while statement.
This conflicts with checkpatch, and the warning should then be ignored.
Change-Id: I22589b68b03f19a426d3bcbc10a99d4e4c76eced
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 11 Mar 2019
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fdts: stm32mp1: add bsec node
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This node is added in a new file stm32mp157c-security.dtsi.
This node includes OTPs that should be shadowed and made readable
to non secure world.
Explicitly add status and secure-status, as these OTPs are accessible
by secure and non-secure world.
The stgen node is also moved to this file.
Change-Id: I3c89a01588d2e411fecfc44997e1c5df2fc37cad
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 11 Mar 2019
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| 2019-03-08 |
allwinner: regulators: pick correct DT subnode
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So far the DT node describing the AXP803 PMIC used in many Allwinner A64
boards had only one subnode, so our code just entering the first subnode
to find all regulators worked fine.
However recent DT updates in the Linux kernel add more subnodes *before*
that, so we need to make sure to explicitly enter the "regulators"
subnode to find the information we are after.
Improve some DT node parsing error handling on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara
authored
on 17 Feb 2019
Dimitris Papastamos
committed
on 8 Mar 2019
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Fixup register handling in aarch32 reset_handler
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The BL handover interface stores the bootloader arguments in
registers r9-r12, so when the reset_handler stores the lr pointer
in r10 it clobers one of the arguments.
Adapt to use r8 and adapt the comment about registers allowed
to clober.
I've checked aarch32 reset_handlers and none seem to use higher
registers as far as I can tell.
Fixes: a6f340fe58b9 ("Introduce the new BL handover interface")
Cc: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner
authored
on 5 Mar 2019
Dimitris Papastamos
committed
on 8 Mar 2019
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zynqmp: pm: Add support for setting PMU configuration object
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Allow EL2 (e.g. U-Boot) to load the configuration object at runtime
into the Xilinx ZynqMP PMU firmware. This allows booting with U-Boot
and U-Boot SPL with PMU FW without hard-coding the configuration
object.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Luca Ceresoli
authored
on 28 Feb 2019
Dimitris Papastamos
committed
on 8 Mar 2019
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mmc: stm32_sdmmc2: fill ocr_voltage
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STM32MP1 SDMMC device voltage is 3.3V. We should then precise the 2 ranges
3.2 to 3.3V and 3.3 to 3.4V in ocr_voltage field.
Change-Id: I88e479f8f16bfe608a7808eace0df3fdec48deab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 8 Mar 2019
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Merge pull request #1867 from AlexeiFedorov/af/enable_ptrauth_warm_boot
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BL31: Enable pointer authentication support in warm boot path
Dimitris Papastamos
authored
on 8 Mar 2019
GitHub
committed
on 8 Mar 2019
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Merge pull request #1870 from thloh85-intel/s10_mmc
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plat: intel: Add MMC OCR voltage information for initialization
Dimitris Papastamos
authored
on 8 Mar 2019
GitHub
committed
on 8 Mar 2019
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Merge pull request #1863 from thloh85-intel/mmc_fixes
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drivers: mmc: Fix some issues with MMC stack
Dimitris Papastamos
authored
on 8 Mar 2019
GitHub
committed
on 8 Mar 2019
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| 2019-03-07 |
plat: intel: Add MMC OCR voltage information for initialization
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MMC stack needs OCR voltage information for the platform to initialize
MMC controller correctly.
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Tien Hock, Loh
committed
on 7 Mar 2019
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