2016-03-04 |
fip_create: miscellaneous improvements to source code
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This patch introduces the following improvements:
* Global variables in fip_create.c declared static.
* Flags to signal the requested actions (do_dump, do_pack) made
global.
* The ToC is printed at the end of the main funcion, after the FIP
has been created/updated, not in the parse_cmdline() function.
* Short format added to the command line options (-d,--dump;
-h,--help).
* Help message updated.
Change-Id: I5f08273c76f1de45fe597e290bee4b60aa404df9
Juan Castillo
committed
on 4 Mar 2016
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2016-02-09 |
Merge pull request #516 from vikramkanigiri/vk/ccn-fix-dvm-entry
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Bug fix: Rectify logic to enter or exit from DVM domain
danh-arm
committed
on 9 Feb 2016
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Merge pull request #515 from soby-mathew/sm/gcc_false_positive
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PSCI: Resolve GCC static analysis false positive
danh-arm
committed
on 9 Feb 2016
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Merge pull request #514 from sandrine-bailleux/sb/a53-a57-disable-non-temporal-hint
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Disable non-temporal hint on Cortex-A53/57
danh-arm
committed
on 9 Feb 2016
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2016-02-08 |
Bug fix: Rectify logic to enter or exit from DVM domain
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Currently, `ccn_snoop_dvm_domain_common()` is responsible for providing
a bitmap of HN-F and HN-I nodes in the interconnect. There is a request
node (RN) corresponding to the master interface (e.g. cluster) that needs
to be added or removed from the snoop/DVM domain. This request node is
removed from or added to each HN-F or HN-I node present in the bitmap
depending upon the type of domain.
The above logic is incorrect when participation of a master interface in
the DVM domain has to be managed. The request node should be removed
from or added to the single Miscellaneous Node (MN) in the system
instead of each HN-I node.
This patch fixes this by removing the intermediate
`ccn_snoop_dvm_domain_common()` and instead reads the MN registers to
get the needed node Id bitmap for snoop(HN-F bitmap) and DVM(MN bitmap)
domains.
Additionally, it renames `MN_DDC_SET_OFF` to `MN_DDC_SET_OFFSET` to
be inline with other macros.
Change-Id: Id896046dd0ccc5092419e74f8ac85e31b104f7a4
Vikram Kanigiri
committed
on 8 Feb 2016
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PSCI: Resolve GCC static analysis false positive
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When BL31 is compiled at `-O3` optimization level using Linaro GCC 4.9
AArch64 toolchain, it reports the following error:
```
services/std_svc/psci/psci_common.c: In function 'psci_do_state_coordination':
services/std_svc/psci/psci_common.c:220:27: error: array subscript is above
array bounds [-Werror=array-bounds]
psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
^
```
This error is a false positive and this patch resolves the error by asserting
the array bounds in `psci_do_state_coordination()`.
Fixes ARM-software/tf-issues#347
Change-Id: I3584ed7b2e28faf455b082cb3281d6e1d11d6495
Soby Mathew
committed
on 8 Feb 2016
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Cortex-Axx: Unconditionally apply CPU reset operations
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In the Cortex-A35/A53/A57 CPUs library code, some of the CPU specific
reset operations are skipped if they have already been applied in a
previous invocation of the reset handler. This precaution is not
required, as all these operations can be reapplied safely.
This patch removes the unneeded test-before-set instructions in
the reset handler for these CPUs.
Change-Id: Ib175952c814dc51f1b5125f76ed6c06a22b95167
Sandrine Bailleux
committed
on 8 Feb 2016
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Disable non-temporal hint on Cortex-A53/57
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The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.
This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.
The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.
Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
Sandrine Bailleux
committed
on 8 Feb 2016
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2016-02-01 |
Merge pull request #511 from soby-mathew/sm/psci_on_race_v2
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Fix PSCI CPU ON race when setting state to ON_PENDING
danh-arm
committed
on 1 Feb 2016
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Merge pull request #508 from soby-mathew/sm/debug_xlat
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Use tf_printf() for debug logs from xlat_tables.c
danh-arm
committed
on 1 Feb 2016
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Merge pull request #504 from sandrine-bailleux/sb/fix-doc-mmap
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Porting Guide: Clarify identity-mapping requirement
danh-arm
committed
on 1 Feb 2016
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Merge pull request #503 from sandrine-bailleux/sb/clarify-doc-el3-payloads
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Clarify EL3 payload documentation
danh-arm
committed
on 1 Feb 2016
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Merge pull request #501 from jcastillo-arm/jc/tf-issues/300
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Disable PL011 UART before configuring it
danh-arm
committed
on 1 Feb 2016
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Fix PSCI CPU ON race when setting state to ON_PENDING
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When a CPU is powered down using PSCI CPU OFF API, it disables its caches
and updates its `aff_info_state` to OFF. The corresponding cache line is
invalidated by the CPU so that the update will be observed by other CPUs
running with caches enabled. There is a possibility that another CPU
which has been trying to turn ON this CPU via PSCI CPU ON API,
has already seen the update to `aff_info_state` and proceeds to update
the state to ON_PENDING prior to the cache invalidation. This may result
in the update of the state to ON_PENDING being discarded.
This patch fixes this issue by making sure that the update of `aff_info_state`
to ON_PENDING sticks by reading back the value after the cache flush and
retrying it if not updated. The patch also adds a dsbish() to
`psci_do_cpu_off()` to ensure ordering of the update to `aff_info_state`
prior to cache line invalidation.
Fixes ARM-software/tf-issues#349
Change-Id: I225de99957fe89871f8c57bcfc243956e805dcca
Soby Mathew
committed
on 1 Feb 2016
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Merge pull request #497 from mtk09422/spm-v3
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update SPM/DCM/MTCMOS related code for power control logic
danh-arm
committed
on 1 Feb 2016
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Use tf_printf() for debug logs from xlat_tables.c
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The debug prints used to debug translation table setup in xlat_tables.c
used the `printf()` standard library function instead of the stack
optimized `tf_printf()` API. DEBUG_XLAT_TABLE option was used to enable
debug logs within xlat_tables.c and it configured a much larger stack
size for the platform in case it was enabled. This patch modifies these
debug prints within xlat_tables.c to use tf_printf() and modifies the format
specifiers to be compatible with tf_printf(). The debug prints are now enabled
if the VERBOSE prints are enabled in Trusted Firmware via LOG_LEVEL build
option.
The much larger stack size definition when DEBUG_XLAT_TABLE is defined
is no longer required and the platform ports are modified to remove this
stack size definition.
Change-Id: I2f7d77ea12a04b827fa15e2adc3125b1175e4c23
Soby Mathew
committed
on 1 Feb 2016
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2016-01-29 |
Porting Guide: Clarify identity-mapping requirement
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The memory translation library in Trusted Firmware supports
non-identity mappings for Physical to Virtual addresses since commit
f984ce84ba. However, the porting guide hasn't been updated
accordingly and still mandates the platform ports to use
identity-mapped page tables for all addresses.
This patch removes this out-dated information from the Porting Guide
and clarifies in which circumstances non-identity mapping may safely
be used.
Fixes ARM-software/tf-issues#258
Change-Id: I84dab9f3cabfc43794951b1828bfecb13049f706
Sandrine Bailleux
committed
on 29 Jan 2016
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Clarify EL3 payload documentation
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This patch reworks the section about booting an EL3 payload in the
User Guide:
- Centralize all EL3 payload related information in the same
section.
- Mention the possibility to program the EL3 payload in flash memory
and execute it in place.
- Provide model parameters for both the Base and Foundation FVPs.
- Provide some guidance to boot an EL3 payload on Juno.
Change-Id: I975c8de6b9b54ff4de01a1154cba63271d709912
Sandrine Bailleux
committed
on 29 Jan 2016
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2016-01-26 |
mt8173: Fix long latency issue of mtcmos contorl
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We found sometimes mtcmos operation is too long in spm (>1ms),
so update a new version to fix it.
I verified with 5 hours power_LoadTest, every mtcmos control
can finish in 500us (average is 100~200us).
Change-Id: I47b712bf9898870f4abcecbea47e01b9786231d4
Signed-off-by: Fan Chen <fan.chen@mediatek.com>
Fan Chen
authored
on 7 Dec 2015
Yidi Lin
committed
on 26 Jan 2016
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mt8173: Improve performance by handling more interrupts during idle
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1. Set more wakeup source
2. Update PCM code for control logic
Change-Id: I2ad06bd85bd1c75a22c838eab4cf5566c443b89a
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Weiyi Lu
authored
on 20 Nov 2015
Yidi Lin
committed
on 26 Jan 2016
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mt8173: Implement subsystem power control logic in ARM TF
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1. Add SiP calls for subsystem power on/off and check support
2. Add subsystem power control related initialization in
bl31_plat_setup.c
3. Add subsystem power on/off and power ack waiting functions
4. Update PCM code for subsystem physical power control logic
Change-Id: Ia0ebb1964c8f9758159bcf17c1813d76ef52cf64
Signed-off-by: yt.lee <yt.lee@mediatek.com>
Jimmy Huang
authored
on 16 Nov 2015
Yidi Lin
committed
on 26 Jan 2016
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mt8173: support big/Little cluster power off for CPU idle(C2 state)
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1. add power control for both big and Little cluster in MCDI
2. fix incorrect PCM_HOTPLUG_VALID_MASK in spm_hotplug.c
3. check the power status of cpus in cluster before setting the cputop
power control
Change-Id: Ifa85306a8bc218098667247904d281494c2f7bfe
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Jimmy Huang
authored
on 16 Nov 2015
Yidi Lin
committed
on 26 Jan 2016
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mt8173: Move SPM related PLL settings to ARM TF
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Move SPM related PLL settings to spm_boot_init in ARM TF SPM driver
Change-Id: I414b896caae072570c8de33a25e06db4ae011f57
Signed-off-by: yt.lee <yt.lee@mediatek.com>
Jimmy Huang
authored
on 16 Nov 2015
Yidi Lin
committed
on 26 Jan 2016
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mt8173: Fix USB remote wake up problem
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This patch updates SPM driver settings and PCM code to fix USB remote
wake up problem.
Change-Id: I07a81cc64b1d226d111380580d09ae25879f4285
Signed-off-by: yt.lee <yt.lee@mediatek.com>
Jimmy Huang
authored
on 16 Nov 2015
Yidi Lin
committed
on 26 Jan 2016
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mt8173: Enable dynamic clock management
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This patch enables dynamic clock management control to reduce power
consumption in various components.
Change-Id: I8f66d9b72c8b1d70169ffe46cc361b16a0dadb77
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Jimmy Huang
authored
on 16 Nov 2015
Yidi Lin
committed
on 26 Jan 2016
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2016-01-25 |
Merge pull request #496 from Xilinx/attr-deprecated
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cdefs.h: Use __deprecated__ instead of deprecated
danh-arm
committed
on 25 Jan 2016
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Merge pull request #495 from jcastillo-arm/jc/tf-issues/170
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ARM plat: add build option to unlock access to non-secure timer
danh-arm
committed
on 25 Jan 2016
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2016-01-21 |
Disable PL011 UART before configuring it
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The PL011 TRM (ARM DDI 0183G) specifies that the UART must be
disabled before any of the control registers are programmed. The
PL011 driver included in TF does not disable the UART, so the
initialization in BL2 and BL31 is violating this requirement
(and potentially in BL1 if the UART is enabled after reset).
This patch modifies the initialization function in the PL011
console driver to disable the UART before programming the
control registers.
Register clobber list and documentation updated.
Fixes ARM-software/tf-issues#300
Change-Id: I839b2d681d48b03f821ac53663a6a78e8b30a1a1
Juan Castillo
committed
on 21 Jan 2016
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2016-01-20 |
cdefs.h: Use __deprecated__ instead of deprecated
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Use the form with underscores to define the '__deprecated' macro to avoid
collisions with potentially defined macros, as suggested in gcc docs
(https://gcc.gnu.org/onlinedocs/gcc/Attribute-Syntax.html#Attribute-Syntax).
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann
committed
on 20 Jan 2016
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ARM plat: add build option to unlock access to non-secure timer
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Currently, Trusted Firmware on ARM platforms unlocks access to the
timer frame registers that will be used by the Non-Secure world. This
unlock operation should be done by the Non-Secure software itself,
instead of relying on secure firmware settings.
This patch adds a new ARM specific build option 'ARM_CONFIG_CNTACR'
to unlock access to the timer frame by setting the corresponding
bits in the CNTACR<N> register. The frame id <N> is defined by
'PLAT_ARM_NSTIMER_FRAME_ID'. Default value is true (unlock timer
access).
Documentation updated accordingly.
Fixes ARM-software/tf-issues#170
Change-Id: Id9d606efd781e43bc581868cd2e5f9c8905bdbf6
Juan Castillo
committed
on 20 Jan 2016
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