Merge pull request #1001 from davidcunado-arm/dc/fix-signed-comparisons ...

Resolve signed-unsigned comparison issues

Merge pull request #978 from etienne-lms/minor-build ...

Minor build fixes

Merge pull request #1000 from dp-arm/dp/aarch32-boot ...

juno/aarch32: Fix boot on Cortex A57 and A72

Resolve signed-unsigned comparison issues ...

A recent commit 030567e added U()/ULL()
macro to TF constants. This has caused some signed-unsigned comparison
warnings / errors in the TF static analysis.

This patch addresses these issues by migrating impacted variables from
signed ints to unsigned ints and vice verse where applicable.

Change-Id: I4b4c739a3fa64aaf13b69ad1702c66ec79247e53
Signed-off-by: David Cunado <david.cunado@arm.com>

Merge pull request #999 from douglas-raillard-arm/dr/fix_tegra_CFLAGS ...

Fix Tegra CFLAGS usage

juno: Invalidate all caches before warm reset to AArch32 state. ...

On Juno AArch32, the L2 cache may contain garbage after the warm reset
from AArch64 to AArch32.  This is all fine until the MMU is configured
and the data caches enabled.  To avoid fetching stale data from the L2
unified cache, invalidate it before the warm reset to AArch32 state.

Change-Id: I7d27e810692c02c3e83c9f31de67f6bae59a960a
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

juno/aarch32: Restore `SCP_BOOT_CFG_ADDR` to the cold boot value ...

Before BL2 loads the SCP ram firmware, `SCP_BOOT_CFG_ADDR` specifies
the primary core.  After the SCP ram firmware has started executing,
`SCP_BOOT_CFG_ADDR` is modified.  This is not normally an issue but
the Juno AArch32 boot flow is a special case.  BL1 does a warm reset
into AArch32 and the core jumps to the `sp_min` entrypoint.  This is
effectively a `RESET_TO_SP_MIN` configuration.  `sp_min` has to be
able to determine the primary core and hence we need to restore
`SCP_BOOT_CFG_ADDR` to the cold boot value before `sp_min` runs.

This magically worked when booting on A53 because the core index was
zero and it just so happened to match with the new value in
`SCP_BOOT_CFG_ADDR`.

Change-Id: I105425c680cf6238948625c1d1017b01d3517c01
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

Merge pull request #994 from soby-mathew/sm/fwu_fix ...

Fix FWU and cache helper optimization

Merge pull request #976 from etienne-lms/minor-psci ...

psci: minor fixes in lib

Merge pull request #997 from dp-arm/dp/spe ...

aarch64: Enable Statistical Profiling Extensions for lower ELs

Fix Tegra CFLAGS usage ...

Use TF_CFLAGS instead of CFLAGS, to allow CFLAGS to be overriden from
the make command line.

Change-Id: I3e5726c04bcd0176f232581b8be2c94413374ac7
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

Merge pull request #995 from davidcunado-arm/dc/init_reg ...

Fully initialise essential control registers

io_dummy: correct sparse warnings ...

Include io_dummy.h header file.
Use static for device_type_dummy function.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

io_storage: use unsigned int for index ...

This change avoids warning about type conversion.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

PSCI: use same function prototype as in header file ...

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

delay_timer: correct sparse issues and warnings ...

Use NULL instead of 0 where required.
Include headers to have the prototype of the functions.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

bl1: include bl1_private.h in aarch* files ...

This change avoids warnings when setting -Wmissing-prototypes or when
using sparse tool.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

context_mgmt: declare extern cm_set_next_context() for AArch32 ...

This change avoids warning when setting -Wmissing-prototypes to
compile bl1_context_mgmt.c.

Reported-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

bl: security_state should be of type unsigned int ...

security_state is either 0 or 1. Prevent sign conversion potential
error (setting -Werror=sign-conversion results in a build error).

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

psci: minor fixes in lib ...

Call svc_suspend_finish if registered.
psci_get_stat() is static to psci_stat.c
Fix types used in comparison.
Fix coding style (empty line between variable definition and instructions
block).

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Merge pull request #996 from dp-arm/dp/aarch32-813419 ...

aarch32: Apply workaround for errata 813419 of Cortex-A57

aarch32: Apply workaround for errata 813419 of Cortex-A57 ...

TLBI instructions for monitor mode won't have the desired effect under
specific circumstances in Cortex-A57 r0p0. The workaround is to
execute DSB and TLBI twice each time.

Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.

The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.

NOTE: This workaround is present in AArch64 TF and already enabled by
default on Juno.

Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

Merge pull request #990 from masahir0y/uniphier ...

uniphier: embed ROTPK hash into BL1/BL2

Merge pull request #988 from Leo-Yan/fix_cpu_off_v1 ...

plat: Hikey960: fix the CPU hotplug

aarch64: Enable Statistical Profiling Extensions for lower ELs ...

SPE is only supported in non-secure state.  Accesses to SPE specific
registers from SEL1 will trap to EL3.  During a world switch, before
`TTBR` is modified the SPE profiling buffers are drained.  This is to
avoid a potential invalid memory access in SEL1.

SPE is architecturally specified only for AArch64.

Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

Fully initialise essential control registers ...

This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.

The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.

This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.

This patch also corrects the following typos:

"NASCR definitions" -> "NSACR definitions"

Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>

Exit early if size zero for cache helpers ...

This patch enables cache helper functions `flush_dcache_range`,
`clean_dcache_range` and `invalidate_dcache_range` to exit early
if the size argument specified is zero

Change-Id: I0b63e8f4bd3d47ec08bf2a0b0b9a7ff8a269a9b0
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Fix issues in FWU code ...

This patch fixes the following issues in Firmware Update (FWU) code:

1. The FWU layer maintains a list of loaded image ids and
   while checking for image overlaps, INVALID_IMAGE_IDs were not
   skipped. The patch now adds code to skip INVALID_IMAGE_IDs.

2. While resetting the state corresponding to an image, the code
   now resets the memory used by the image only if the image were
   copied previously via IMAGE_COPY smc. This prevents the invalid
   zeroing of image memory which are not copied but are directly
   authenticated via IMAGE_AUTH smc.

Change-Id: Idf18e69bcba7259411c88807bd0347d59d9afb8f
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Merge pull request #983 from dp-arm/dp/aarch32-errata ...

aarch32: Implement errata workarounds for Cortex A53 and A57

uniphier: embed ROTPK hash into BL1/BL2 ...

Currently, ROTPK_NOT_DEPLOYED flag is set in plat_get_rotpk_info().
It is up to users how to retrieve ROTPK if the ROT verification is
desired.  This is not nice.

This commit improves plat_get_rotpk_info() implementation and automates
the ROTPK deployment.  UniPhier platform has no ROTPK storage, so it
should be embedded in BL1/BL2, like ARM_ROTPK_LOCATION=devel_rsa case.
This makes sense because UniPhier platform implements its internal ROM
i.e. BL1 is used as updatable pseudo ROM.

Things work like this:

- ROT_KEY (default: $(BUILD_PLAT)/rot_key.pem) is created if missing.
  Users can override ROT_KEY from the command line if they want to
  use a specific ROT key.

- ROTPK_HASH is generated based on ROT_KEY.

- ROTPK_HASH is included by uniphier_rotpk.S and compiled into BL1/BL2.

- ROT_KEY is input to cert_create tool.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>