2015-06-19 |
Fix incorrect assertions in bl1_main()
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The validation of the caching enable state in bl1_main() was
incorrect resulting in the state not being checked. Using the right
operator fixes this.
Change-Id: I2a99478f420281a1dcdf365d3d4fd8394cd21b51
Andrew Thoelke
committed
on 19 Jun 2015
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2015-06-12 |
Merge pull request #317 from vwadekar/run-bl32-on-tegra-v3
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Run bl32 on tegra v3
Achin Gupta
committed
on 12 Jun 2015
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2015-06-11 |
Move dispatcher documents to the docs/spd folder
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This patch moves the optee-dispatcher.md and tlk-dispatcher.md to
docs/spd.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 11 Jun 2015
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Boot Trusted OS' on Tegra SoCs
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This patch adds support to run a Trusted OS during boot time. The
previous stage bootloader passes the entry point information in
the 'bl32_ep_info' structure, which is passed over to the SPD.
The build system expects the dispatcher to be passed as an input
parameter using the 'SPD=<dispatcher>' option. The Tegra docs have
also been updated with this information.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 11 Jun 2015
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2015-06-09 |
Merge pull request #314 from sandrine-bailleux/sb/css-data-structs
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Clarify some CSS data structures
danh-arm
committed
on 9 Jun 2015
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Merge pull request #312 from jcastillo-arm/jc/tf-issues/308
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Fix build option 'ARM_TSP_RAM_LOCATION' in user guide
danh-arm
committed
on 9 Jun 2015
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CSS: Remove the constants MHU_SECURE_BASE/SIZE
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For CSS based platforms, the constants MHU_SECURE_BASE and
MHU_SECURE_SIZE used to define the extents of the Trusted Mailboxes.
As such, they were misnamed because the mailboxes are completely
unrelated to the MHU hardware.
This patch removes the MHU_SECURE_BASE and MHU_SECURE_SIZE #defines.
The address of the Trusted Mailboxes is now relative to the base of
the Trusted SRAM.
This patch also introduces a new constant, SCP_COM_SHARED_MEM_BASE,
which is the address of the first memory region used for communication
between AP and SCP. This is used by the BOM and SCPI protocols.
Change-Id: Ib200f057b19816bf05e834d111271c3ea777291f
Sandrine Bailleux
committed
on 9 Jun 2015
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CSS: Clarify what the SCP boot config is
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Add a comment explaining what the SCP boot configuration information
is on CSS based platforms like Juno. Also express its address
relatively to the base of the Trusted SRAM rather than hard-coding it.
Change-Id: I82cf708a284c8b8212933074ea8c37bdf48b403b
Sandrine Bailleux
committed
on 9 Jun 2015
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2015-06-08 |
Fix build option 'ARM_TSP_RAM_LOCATION' in user guide
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The 'ARM_TSP_RAM_LOCATION_ID' option specified in the user guide
corresponds to the internal definition not visible to the final
user. The proper build option is 'ARM_TSP_RAM_LOCATION'. This
patch fixes it.
Fixes ARM-software/tf-issues#308
Change-Id: Ica8cb72c0c5e8b3503f60b5357d16698e869b1bd
Juan Castillo
committed
on 8 Jun 2015
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2015-06-05 |
Merge pull request #309 from soby-mathew/sm/fix_fvp_get_entry
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FVP: Correct the PSYSR_WK bit width in platform_get_entrypoint
danh-arm
committed
on 5 Jun 2015
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2015-06-03 |
FVP: Correct the PSYSR_WK bit width in platform_get_entrypoint
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This patch fixes the incorrect bit width used to extract the wakeup
reason from PSYSR in platform_get_entrypoint() function. This defect
did not have any observed regression.
Change-Id: I42652dbffc99f5bf50cc86a5878f28d730720d9a
Soby Mathew
committed
on 3 Jun 2015
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2015-06-02 |
Merge pull request #305 from achingupta/ag/tf-issues#306
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Ag/tf issues#306
Achin Gupta
committed
on 2 Jun 2015
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Merge pull request #307 from soby-mathew/sm/css_bit_width_fix
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CSS: Extract primary cpu id using the correct bit width
Achin Gupta
committed
on 2 Jun 2015
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Merge pull request #308 from vwadekar/tegra-soc-support-v4
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Tegra soc support v4
Achin Gupta
committed
on 2 Jun 2015
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2015-05-29 |
Support for NVIDIA's Tegra T210 SoCs
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T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.
This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 29 May 2015
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Driver for 16550 UART interface
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This patch adds driver for the 16550 UART interface. The driver is exposed
as a console, which platforms can use to dump their boot/crash logs.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 29 May 2015
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2015-05-27 |
CSS: Extract primary cpu id using the correct bit width
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This patch fixes the incorrect bit width used to extract the primary
cpu id from `ap_data` exported by scp at SCP_BOOT_CFG_ADDR in
platform_is_primary_cpu().
Change-Id: I14abb361685f31164ecce0755fc1a145903b27aa
Soby Mathew
committed
on 27 May 2015
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2015-05-20 |
Merge pull request #303 from danh-arm/dh/fix-fvp-setup-topology
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Fix return type of FVP plat_arm_topology_setup
danh-arm
committed
on 20 May 2015
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2015-05-19 |
Fix reporting of interrupt ID in ARM GIC driver
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The ARM GIC driver treats the entire contents of the GICC_HPPIR as the interrupt
ID instead of just bits[9:0]. This could result in an SGI being treated as a
Group 1 interrupt on a GICv2 system.
This patch introduces a mask to retrieve only the ID from a read of GICC_HPPIR,
GICC_IAR and similar registers. The value read from these registers is masked
with this constant prior to use as an interrupt ID.
Fixes ARM-software/tf-issues#306
Change-Id: Ie3885157de33b71df9781a41f6ef015a30c4608d
Achin Gupta
committed
on 19 May 2015
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Fix return type of FVP plat_arm_topology_setup
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Fix the return type of the FVP `plat_arm_topology_setup` function
to be `void` instead of `int` to match the declaration in
`plat_arm.h`.
This does not result in any change in behavior.
Change-Id: I62edfa7652b83bd26cffb7d167153959b38e37e7
Dan Handley
committed
on 19 May 2015
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2015-05-18 |
Merge pull request #301 from soby-mathew/sm/cpu_on_pend_state_fix
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PSCI: Set ON_PENDING state early during CPU_ON
achingupta
committed
on 18 May 2015
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2015-05-13 |
Fix handling of spurious interrupts in BL3_1
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There are couple of issues with how the interrupt routing framework in BL3_1
handles spurious interrupts.
1. In the macro 'handle_interrupt_exception', if a spurious interrupt is
detected by plat_ic_get_pending_interrupt_type(), then execution jumps to
'interrupt_exit_\label'. This macro uses the el3_exit() function to return to
the original exception level. el3_exit() attempts to restore the SPSR_EL3 and
ELR_EL3 registers with values from the current CPU context. Since these
registers were not saved in this code path, it programs stale values into
these registers. This leads to unpredictable behaviour after the execution of
the ERET instruction.
2. When an interrupt is routed to EL3, it could be de-asserted before the
GICC_HPPIR is read in plat_ic_get_pending_interrupt_type(). There could be
another interrupt pending at the same time e.g. a non-secure interrupt. Its
type will be returned instead of the original interrupt. This would result in
a call to get_interrupt_type_handler(). The firmware will panic if the
handler for this type of interrupt has not been registered.
This patch fixes the first problem by saving SPSR_EL3 and ELR_EL3 early in the
'handle_interrupt_exception' macro, instead of only doing so once the validity
of the interrupt has been determined.
The second problem is fixed by returning execution back to the lower exception
level through the 'interrupt_exit_\label' label instead of treating it as an
error condition. The 'interrupt_error_\label' label has been removed since it is
no longer used.
Fixes ARM-software/tf-issues#305
Change-Id: I81c729a206d461084db501bb81b44dff435021e8
Achin Gupta
committed
on 13 May 2015
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PSCI: Set ON_PENDING state early during CPU_ON
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In the debug build of the function get_power_on_target_afflvl(), there is a
check to ensure that the CPU is emerging from a SUSPEND or ON_PENDING state.
The state is checked without acquiring the lock for the CPU node. The state
could be updated to ON_PENDING in psci_afflvl_on() after the target CPU has
been powered up. This results in a race condition which could cause the
check for the ON_PENDING state in get_power_on_target_afflvl() to fail.
This patch resolves this race condition by setting the state of the target
CPU to ON_PENDING before the platform port attempts to power it on. The
target CPU is thus guaranteed to read the correct the state. In case
the power on operation fails, the state of the CPU is restored to OFF.
Fixes ARM-software/tf-issues#302
Change-Id: I3f2306a78c58d47b1a0fb7e33ab04f917a2d5044
Soby Mathew
committed
on 13 May 2015
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2015-04-29 |
Merge pull request #297 from sandrine-bailleux/sb/move-up-deps
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Move up dependency versions
danh-arm
committed
on 29 Apr 2015
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Merge pull request #296 from danh-arm/sb/scpi-min-changes
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Move to the new ARM SCP Messaging Interfaces v2
danh-arm
committed
on 29 Apr 2015
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Merge pull request #295 from danh-arm/dh/plat-port-reorg
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ARM platform port reorganization
danh-arm
committed
on 29 Apr 2015
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FVP: update device tree idle state entries
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Device tree idle state bindings changed in kernel v3.18. This patch
updates the FVP DT files to use PSCI suspend as idle state.
The patch also updates the 'compatible' property in the PSCI node
and the 'entry-method' property in the idle-states node in the FVP
Foundation GICv2-legacy device tree.
Change-Id: Ie921d497c579f425c03d482f9d7b90e166106e2f
Juan Castillo
authored
on 16 Apr 2015
Sandrine Bailleux
committed
on 29 Apr 2015
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Move up dependency versions in user guide
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Move up the version numbers in the user guide of:
* DS-5 (to v5.21)
* EDK2 (to v3.0)
* Linux Kernel (to 1.6-Juno)
* Linaro file-system (to 15.03)
* Juno SCP binary (to v1.7.0 within board recovery image 0.11.3).
Change-Id: Ieb09e633acc2b33823ddf35f77f44e7da60b99ba
Sandrine Bailleux
committed
on 29 Apr 2015
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2015-04-28 |
Detect SCP version incompatibility
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There has been a breaking change in the communication protocols used
between the AP cores and the SCP on CSS based platforms like Juno.
This means both the AP Trusted Firmware and SCP firmware must be
updated at the same time.
In case the user forgets to update the SCP ROM firmware, this patch
detects when it still uses the previous version of the communication
protocol. It will then output a comprehensive error message that helps
trouble-shoot the issue.
Change-Id: I7baf8f05ec0b7d8df25e0ee53df61fe7be0207c2
Sandrine Bailleux
authored
on 13 Apr 2015
Dan Handley
committed
on 28 Apr 2015
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Move to the new ARM SCP Messaging Interfaces
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The communication protocol used between the AP cores and the SCP
in CSS-based platforms like Juno has undergone a number of changes.
This patch makes the required modifications to the SCP Boot Protocol,
SCPI Protocol and MHU driver code in shared CSS platform code so that
the AP cores are still able to communicate with the SCP.
This patch focuses on the mandatory changes to make it work. The
design of this code needs to be improved but this will come in
a subsequent patch.
The main changes are:
- MHU communication protocol
- The command ID and payload size are no longer written into the
MHU registers directly. Instead, they are stored in the payload
area. The MHU registers are now used only as a doorbell to kick
off messages. Same goes for any command result, the AP has to
pick it up from the payload area.
- SCP Boot Protocol
- The BL3-0 image is now expected to embed a checksum. This
checksum must be passed to the SCP, which uses it to check the
integrity of the image it received.
- The BL3-0 image used to be transferred a block (4KB)
at a time. The SCP now supports receiving up to 128KB at a
time, which is more than the size of the BL3-0 image.
Therefore, the image is now sent in one go.
- The command IDs have changed.
- SCPI Protocol
- The size of the SCPI payload has been reduced down from 512
bytes to 256 bytes. This changes the base address of the
AP-to-SCP payload area.
- For commands that have a response, the response is the same SCPI
header that was sent, except for the size and the status, which
both must be updated appropriately. Success/Failure of a command
is determined by looking at the updated status code.
- Some command IDs have changed.
NOTE: THIS PATCH BREAKS COMPATIBILITY WITH FORMER VERSIONS OF THE SCP
FIRMWARE AND THUS REQUIRES AN UPDATE OF THIS BINARY. THE LATEST SCP
BINARY CAN BE OBTAINED FROM THE ARM CONNECTED COMMUNITY WEBSITE.
Change-Id: Ia5f6b95fe32401ee04a3805035748e8ef6718da7
Sandrine Bailleux
authored
on 18 Mar 2015
Dan Handley
committed
on 28 Apr 2015
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