Give user's compiler flags precedence over default ones ...

The user can provide additional CFLAGS to use when building TF.
However, these custom CFLAGS are currently prepended to the
standard CFLAGS that are hardcoded in the TF build system. This
is an issue because when providing conflicting compiler flags
(e.g. different optimisations levels like -O1 and -O0), the last
one on the command line usually takes precedence. This means that
the user flags get overriden.

To address this problem, this patch separates the TF CFLAGS from
the user CFLAGS. The former are now stored in the TF_CFLAGS make
variable, whereas the CFLAGS make variable is untouched and reserved
for the user. The order of the 2 sets of flags is enforced when
invoking the compiler.

Fixes ARM-Software/tf-issues#350

Change-Id: Ib189f44555b885f1dffbec6015092f381600e560

Merge pull request #590 from yatharth-arm/yk/tzc400 ...

Use unsigned long long instead of uintptr_t in TZC400/DMC500 drivers

Use unsigned long long instead of uintptr_t in TZC400/DMC500 drivers ...

Currently the `tzc400_configure_region` and `tzc_dmc500_configure_region`
functions uses uintptr_t as the data type for `region_top` and `region_base`
variables, which will be converted to 32/64 bits for AArch32/AArch64
respectively. But the expectation is to keep these addresses at least 64 bit.

This patch modifies the data types to make it at least 64 bit by using
unsigned long long instead of uintptr_t for the `region_top` and
`region_base` variables. It also modifies the associated macros
`_tzc##fn_name##_write_region_xxx` accordingly.

Change-Id: I4e3c6a8a39ad04205cf0f3bda336c3970b15a28b

Merge pull request #589 from soby-mathew/sm/fix_rk_build_err ...

Fix build error in Rockchip platform

Fix build error in Rockchip platform ...

This patch fixes the compilation error in Rockchip rk3368 platform port when
it is built in release mode.

Fixes ARM-software/tf-issues#389

Change-Id: I1a3508ac3a620289cf700e79db8f08569331ac53

Merge pull request #579 from ashutoshksingh/master ...

pass r0-r6 as part of smc param

Merge pull request #569 from Xilinx/zynqmp-v1 ...

Support for Xilinx Zynq UltraScale+ MPSoC

Merge pull request #588 from antonio-nino-diaz-arm/an/ignore-check-md ...

Fix style check and remove markdown files from it

Remove markdown files from coding style check ...

All markdown (.md) files in the root directory of the repository and
all the files inside the 'docs' directory have been removed from
ROOT_DIRS_TO_CHECK in the Makefile in order not to perform the coding
style check on them.

Change-Id: Iac397b44f95cbcdb9a52cc20bf69998c394ac00a

Fix list of paths to perform coding style check on ...

Removed an extra parentheses that produced an invalid list of files
and directories to check by checkpatch.pl.

Change-Id: Iefe2c1f8be6e7b7b58f6ffe3e16fe6336b9a8689

Merge pull request #587 from antonio-nino-diaz-arm/an/rename-bl33-base ...

Rename BL33_BASE and make it work with RESET_TO_BL31

Merge pull request #586 from antonio-nino-diaz-arm/an/spd-bl32 ...

Remove BL32_BASE when building without SPD for FVP

Merge pull request #585 from soby-mathew/sm/tf_printf_ll_changes ...

Differentiate `long` and `long long` formats in tf_printf

Rename BL33_BASE option to PRELOADED_BL33_BASE ...

To avoid confusion the build option BL33_BASE has been renamed to
PRELOADED_BL33_BASE, which is more descriptive of what it does and
doesn't get mistaken by similar names like BL32_BASE that work in a
completely different way.

NOTE: PLATFORMS USING BUILD OPTION `BL33_BASE` MUST CHANGE TO THE NEW
BUILD OPTION `PRELOADED_BL33_BASE`.

Change-Id: I658925ebe95406edf0325f15aa1752e1782aa45b

Fix BL33_BASE option to work with RESET_TO_BL31 ...

The BL33 address is now set in arm_bl31_early_platform_setup() so
that the preloaded BL33 boot option is available when RESET_TO_BL31
is also used.

Change-Id: Iab93e3916f9199c3387886b055c7cd2315efed29

Remove BL32_BASE when building without SPD for FVP ...

Previously, when building TF without SPD support, BL2 tried to load a
BL32 image from the FIP and fails to find one, which resulted on
warning messages on the console. Even if there is a BL32 image in the
FIP it shouldn't be loaded because there is no way to transfer
control to the Secure Payload without SPD support.

The Makefile has been modified to pass a define of the form
SPD_${SPD} to the source code the same way it's done for PLAT. The
define SPD_none is then used to undefine BL32_BASE when BL32 is not
used to prevent BL2 from trying to load a BL32 image and failing,
thus removing the warning messages mentioned above.

Fixes ARM-software/tf-issues#287

Change-Id: Ifeb6f1c26935efb76afd353fea88e87ba09e9658

Differentiate `long` and `long long` formats in tf_printf ...

This patch adds support to differentiate between `long` and `long long`
format specifiers in tf_printf(). In AArch64, they are the same which is
a 64-bit word. But, in AArch32 they are different and tf_printf() needs
to handle these format specifiers separately. This patch also fixes the
type of variables used to generic C types.

Change-Id: If3bbb0245cd0183acbe13bc1fe0d9743f417578f

Merge pull request #584 from soby-mathew/sm/enable_scr_sif ...

Enable SCR_EL3.SIF bit

Merge pull request #583 from mtk09422/fix-build-error ...

mt8173: fix spm driver build errors

Merge pull request #582 from jcastillo-arm/jc/fip_extract ...

fip_create: add support for image unpacking

Merge pull request #578 from EvanLloyd/ejll/woa_make2 ...

Make improvements for host environment portability

Merge pull request #575 from soby-mathew/sm/new_tzc_driver ...

Refactor the TZC driver and add DMC-500 driver

Merge pull request #572 from jcastillo-arm/jc/tbb_nvcounter ...

TBB NVcounter support

Merge pull request #563 from sbranden/tf_issue_380 ...

Add support for %z in tf_print()

Enable SCR_EL3.SIF bit ...

This patch enables the SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and
BL31 common architectural setup code. When in secure state, this disables
instruction fetches from Non-secure memory.

NOTE: THIS COULD BREAK PLATFORMS THAT HAVE SECURE WORLD CODE EXECUTING FROM
NON-SECURE MEMORY, BUT THIS IS CONSIDERED UNLIKELY AND IS A SERIOUS SECURITY
RISK.

Fixes ARM-Software/tf-issues#372

Change-Id: I684e84b8d523c3b246e9a5fabfa085b6405df319

mt8173: fix spm driver build errors ...

To fix build errors in following build conditions,
DEBUG=1 LOG_LEVEL<40
DEBUG=0 LOG_LEVEL>=40

Change-Id: Ib34aed07b2ae0abd8a3a46948adc9fbeaae715aa
Signed-off-by: yt.lee <yt.lee@mediatek.com>

Add Xilinx to acknowledgements file ...

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Add support for Xilinx Zynq UltraScale+ MPSOC ...

The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This
patch adds the platform port for that SoC.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

fip_create: add support for image unpacking ...

This patch adds support for image unpacking to the FIP packaging
tool. Command line option '-u,--unpack' may be used to unpack the
contents of an existing FIP file into the working directory. The
tool uses default hardcoded filenames for the unpacked images. If
the files already exist, they can be overwritten by specifying the
option '-f,--force'.

Change-Id: I360b11d9c5403e8c0a7a9cac32c1d90ebb228063

Merge pull request #581 from rockchip-linux/rockchip-atf-20160405 ...

Support for Rockchip's family SoCs