meson: Use generic console_t data structure ...

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I07a07677153d3671ced776671e4f107824d3df16
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

include: move MHZ_TICKS_PER_SEC to utils_def.h ...

This patch moves the MHZ_TICKS_PER_SEC macro to utils_def.h
for other platforms to use.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6c4dc733f548d73cfdb3515ec9ad89a9efaf4407

Merge changes I72846d86,I70c3d873,If675796a,I0dbf8091,Ie4f3ac83, ... into integration ...

* changes:
  rcar_gen3: plat: Minor coding style fix for rcar_version.h
  rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.6
  rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: board: Add new board revision for M3ULCB
  rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
  rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.5
  rcar_gen3: plat: Change fixed destination address of BL31 and BL32

Merge "TBBR: Reduce size of hash buffers when possible" into integration

Merge "TBBR: Reduce size of ECDSA key buffers" into integration

Merge "coverity: fix MISRA violations" into integration

coverity: fix MISRA violations ...

Fixes for the following MISRA violations:
- Missing explicit parentheses on sub-expression
- An identifier or macro name beginning with an
  underscore, shall not be declared
- Type mismatch in BL1 SMC handlers and tspd_main.c

Change-Id: I7a92abf260da95acb0846b27c2997b59b059efc4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>

TBBR: Reduce size of hash buffers when possible ...

The TBBR implementation extracts hashes from certificates and stores
them in static buffers. TF-A supports 3 variants of SHA right now:
SHA-256, SHA-384 and SHA-512. When support for SHA-512 was added in
commit 9a3088a ("tbbr: Add build flag
HASH_ALG to let the user to select the SHA"), the hash buffers got
unconditionally increased from 51 to 83 bytes each. We can reduce that
space if we're using SHA-256 or SHA-384.

This saves some BSS space in both BL1 and BL2:
- BL1 with SHA-256: saving 168 bytes.
- BL1 with SHA-384: saving 80 bytes.
- BL2 with SHA-256: saving 384 bytes.
- BL2 with SHA-384: saving 192 bytes.

Change-Id: I0d02e5dc5f0162e82339c768609c9766cfe7e2bd
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

TBBR: Reduce size of ECDSA key buffers ...

The TBBR implementation extracts public keys from certificates and
stores them in static buffers. DER-encoded ECDSA keys are only 91 bytes
each but were each allocated 294 bytes instead. Reducing the size of
these buffers saves 609 bytes of BSS in BL2 (294 - 91 = 203 bytes for
each of the 3 key buffers in use).

Also add a comment claryfing that key buffers are tailored on RSA key
sizes when both ECDSA and RSA keys are used.

Change-Id: Iad332856e7af1f9814418d012fba3e1e9399f72a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N ...

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.40.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: If675796a2314e769602af21bf5cc6b10962d4f29

rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N ...

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.39.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I0dbf8091f9de9bb6d2d4f94007a5813fff14789f

rcar_gen3: drivers: board: Add new board revision for M3ULCB ...

Board Revision[2:0]
 3'b000 Rev1.0
 3'b011 Rev3.0 [New]

Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: Ie4f3ac83cc20120ede21052f7452327049565e60

rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N ...

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.38.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I49cf8f778b849a6ee97bc9f6948c45b07dc467b1

Merge changes Ib68092d1,I816ea14e into integration ...

* changes:
  plat: marvell: armada: scp_bl2: allow loading up to 8 images
  plat: marvell: armada: add support for loading MG CM3 images

Merge changes from topic "lm/fconf" into integration ...

* changes:
  arm-io: Panic in case of io setup failure
  MISRA fix: Use boolean essential type
  fconf: Add documentation
  fconf: Move platform io policies into fconf
  fconf: Add mbedtls shared heap as property
  fconf: Add TBBR disable_authentication property
  fconf: Add dynamic config DTBs info as property
  fconf: Populate properties from dtb during bl2 setup
  fconf: Load config dtb from bl1
  fconf: initial commit

Merge "coverity: Fix MISRA null pointer violations" into integration

drivers/arm/scmi: allow use of multiple SCMI channels ...

On systems that have multiple platform components that can interpret the
SCMI messages, there is a need to support multiple SCMI channels (one
each to those platform components). Extend the existing SCMI interface
that currently supports only a single SCMI channel to support multiple
SCMI channels.

Change-Id: Ice4062475b903aef3b5e5bc37df364c9778a62c5
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

drivers/mhu: derive doorbell base address ...

In order to allow the MHUv2 driver to be usable with multiple MHUv2
controllers, use the base address of the controller from the platform
information instead of the MHUV2_BASE_ADDR macro.

Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

fconf: initial commit ...

Introduce the Firmware CONfiguration Framework (fconf).

The fconf is an abstraction layer for platform specific data, allowing
a "property" to be queried and a value retrieved without the requesting
entity knowing what backing store is being used to hold the data.

The default backing store used is C structure. If another backing store
has to be used, the platform integrator needs to provide a "populate()"
function to fill the corresponding C structure.
The "populate()" function must be registered to the fconf framework with
the "FCONF_REGISTER_POPULATOR()". This ensures that the function would
be called inside the "fconf_populate()" function.

A two level macro is used as getter:
- the first macro takes 3 parameters and converts it to a function
  call: FCONF_GET_PROPERTY(a,b,c) -> a__b_getter(c).
- the second level defines a__b_getter(c) to the matching C structure,
  variable, array, function, etc..

Ex: Get a Chain of trust property:
    1) FCONF_GET_PROPERY(tbbr, cot, BL2_id) -> tbbr__cot_getter(BL2_id)
    2) tbbr__cot_getter(BL2_id) -> cot_desc_ptr[BL2_id]

Change-Id: Id394001353ed295bc680c3f543af0cf8da549469
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

coverity: Fix MISRA null pointer violations ...

Fix code that violates the MISRA rule:
MISRA C-2012 Rule 11.9: Literal "0" shall not be used as
null pointer constant.

The fix explicitly checks whether a pointer is NULL.

Change-Id: Ibc318dc0f464982be9a34783f24ccd1d44800551
Signed-off-by: Zelalem <zelalem.aweke@arm.com>

Coverity: remove unnecessary header file includes ...

This patch removes unnecessary header file includes
discovered by Coverity HFA option.

Change-Id: I2827c37c1c24866c87db0e206e681900545925d4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>

plat: marvell: armada: add support for loading MG CM3 images ...

In order to access MG SRAM, the amb bridge needs to be configured which is
done in bl2 platform init.

For MG CM3, the image is only loaded to its SRAM and the CM3 itself is
left in reset. It is because the next stage bootloader (e.g. u-boot)
will trigger action which will take it out of reset when needed. This
can happen e.g. when appropriate device-tree setup (which has enabled
802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be
running.

Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

Merge "Use correct type when reading SCR register" into integration

Measured Boot: add function for hash calculation ...

This patch adds 'calc_hash' function using Mbed TLS library
required for Measured Boot support.

Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Use correct type when reading SCR register ...

The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

spi: stm32_qspi: Add QSPI support ...

Add QSPI support (limited to read interface).
Implements the memory map and indirect modes.
Low level driver based on SPI-MEM operations.

Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

fmc: stm32_fmc2_nand: Add FMC2 driver support ...

Add fmc2_nand driver support. The driver implements
only read interface for NAND devices.

Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

Add SPI-NOR framework ...

SPI-NOR framework is based on SPI-MEM framework using
spi_mem_op execution interface.

It implements read functions and allows NOR configuration
up to quad mode.
Default management is 1 data line but it can be overridden
by platform.
It also includes specific quad mode configuration for
Spansion, Micron and Macronix memories.

Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

Add SPI-NAND framework ...

This framework supports SPI-NAND and is based on the
SPI-MEM framework for SPI operations. It uses a common high
level access using the io_mtd.

It is limited to the read functionalities.

Default behavior is the basic one data line operation
but it could be overridden by platform.

Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

Add SPI-MEM framework ...

This framework supports SPI operations using a common
spi_mem_op structure:
 - command
 - addr
 - dummy
 - data

The framework manages SPI bus configuration:
 - speed
 - bus width (Up to quad mode)
 - chip select

Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>