Merge "rk3399: m0: Fix compiler warnings." into integration

Merge "Cortex-A53: Fix reporting of missing errata when not needed" into integration

Merge changes from topic "rk3288" into integration ...

* changes:
  rockchip: document platform
  rockchip: add support for rk3288
  rockchip: add common aarch32 support
  rockchip: rk3328: drop double declaration of entry_point storage
  rockchip: Allow socs with undefined wfe check bits
  rockchip: move pmusram assembler code to a aarch64 subdir
  sp_min: allow inclusion of a platform-specific linker script
  sp_min: make sp_min_warm_entrypoint public
  drivers: ti: uart: add a aarch32 variant

Merge "Doc: Update link to TBBR-CLIENT specification" into integration

Cortex-A53: Fix reporting of missing errata when not needed ...

Errata 819472, 824069, and 827319 are currently reported in a warning as
missing during boot for platforms that do not need them. Only warn when
the errata is needed for a given revision but not compiled in like other
errata workarounds.

Fixes: bd393704d2b1 ("Cortex-A53: Workarounds for 819472, 824069 and 827319")
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ifd757b3d0e73a9bd465b98dc20648b6c13397d8d

rockchip: document platform ...

This adds a rockchip.rst to docs/plat documenting the general
approach to using the Rockchip ATF platforms together with the
supported bootloaders and also adds myself as maintainer after
making sure Tony Xie is ok with that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Idce53d15eff4ac6de05bbb35d86e57ed50d0cbb9

rockchip: add support for rk3288 ...

The rk3288 is a 4-core Cortex-A12 SoC and shares a lot of features
with later SoCs.

Working features are general non-secure mode (the gic needs special
love for that), psci-based smp bringing cpu cores online and also
taking them offline again, psci-based suspend (the simpler variant
also included in the linux kernel, deeper suspend following later)
and I was also already able to test HYP-mode and was able to boot
a virtual kernel using kvm.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ibaaa583b2e78197591a91d254339706fe732476a

rockchip: add common aarch32 support ...

There are a number or ARMv7 Rockchip SoCs that are very similar in their
bringup routines to the existing arm64 SoCs, so there is quite a high
commonality possible here.

Things like virtualization also need psci and hyp-mode and instead of
trying to cram this into bootloaders like u-boot, barebox or coreboot
(all used in the field), re-use the existing infrastructure in TF-A
for this (both Rockchip plat support and armv7 support in general).

So add core support for aarch32 Rockchip SoCs, with actual soc support
following in a separate patch.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I298453985b5d8434934fc0c742fda719e994ba0b

rockchip: rk3328: drop double declaration of entry_point storage ...

The cpuson_entry_point and cpuson_flags are already declared in
plat_private.h so there is no need to have it again declared in
the local pmu.h, especially as it may cause conflicts when the
other type changes.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I80ae0e23d22f67109ed96f8ac059973b6de2ce87

rockchip: Allow socs with undefined wfe check bits ...

Some older socs like the rk3288 do not have the necessary registers
to check the wfi/wfe state of the cpu cores. Allow this case an "just"
do an additional delay similar to how the Linux kernel handles smp
right now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I0f67af388b06b8bfb4a9bac411b4900ac266a77a

rockchip: move pmusram assembler code to a aarch64 subdir ...

The current code doing power-management from sram is highly
arm64-specific so should live in a corresponding subdirectory
and not in the common area.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I3b79ac26f70fd189d4d930faa6251439a644c5d9

sp_min: allow inclusion of a platform-specific linker script ...

Similar to bl31 allow sp_min to also include a platform-specific
linker script. This allows for example to place specific code in
other memories of the system, like resume code in sram, while the
main tf-a lives in ddr.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I67642f7bfca036b5d51eb0fa092b479a647a9cc1

sp_min: make sp_min_warm_entrypoint public ...

Similar to bl31_warm_entrypoint, sp_min-based platforms may need
that for special resume handling.

Therefore move it from the private header to the sp_min platform header.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I40d9eb3ff77cff88d47c1ff51d53d9b2512cbd3e

drivers: ti: uart: add a aarch32 variant ...

Rockchip re-uses the ti uart console driver and for aarch32 needs a
specific variant, so add it.
There are also aarch32 ti socs, so it may be useful for them as well
at some point.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I31ede7cc7b10347b3691cff051db2b985fd59e17

Doc: Update link to TBBR-CLIENT specification ...

Change-Id: Iafa79b6f7891d3eebec9908a8f7725131202beb3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

rk3399: m0: Fix compiler warnings. ...

GCC complains for quite some versions, when compiling the M0 firmware
for Rockchip's rk3399 platform, about an invalid type of function 'main':

  warning: return type of 'main' is not 'int' [-Wmain]

This patch addresses this, by renaming the function to 'm0_main'.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I10887f2bda6bdb48c5017044c264139004f7c785

Merge changes from topic "av/console-register" into integration ...

* changes:
  Console: Remove Arm console unregister on suspend
  Console: Allow to register multiple times

Merge changes from topic "k3-sequence-fix" into integration ...

* changes:
  ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID
  ti: k3: drivers: ti_sci: Cleanup sequence ID usage
  ti: k3: drivers: sec_proxy: Use direction definitions
  ti: k3: drivers: sec_proxy: Fix printf format specifiers

Merge changes from topic "k3-cleanups" into integration ...

* changes:
  ti: k3: common: Align elements of map region table
  ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by default
  ti: k3: common: Remove shared RAM space
  ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines

Console: Remove Arm console unregister on suspend ...

Change-Id: Ie649b3c367a93db057eeaee7e83fa3e43f8c2607
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Console: Allow to register multiple times ...

It removes the need to unregister the console on system suspend.

Change-Id: Ic9311a242a4a9a778651f7e6380bd2fc0964b2ce
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID ...

When we get a sequence ID that does not match what we expect then the we
are looking at is not the one we are expecting and so we error out. We
can also assume this message is a stale message left in the queue, in
this case we can read in the next message and check again for our
message. Switch to doing that here. We only retry a set number of times
so we don't lock the system if our message is actually lost and will
never show up.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I6c8186ccc45e646d3ba9d431f7d4c451dcd70c5c

ti: k3: drivers: ti_sci: Cleanup sequence ID usage ...

The sequence ID can be set with a message to identify it when it is
responded to in the response queue. We assign each message a number and
check for this same number to detect response mismatches.

Start this at 0 and increase it by one for each message sent, even ones
that do not request or wait for a response as one may still be delivered
in some cases and we want to detect this.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I72b4d1ef98bf1c1409d9db9db074af8dfbcd83ea

ti: k3: drivers: sec_proxy: Use direction definitions ...

The direction of a thread should be explicitly compared to avoid
confusion. Also fixup message wording based on this direction.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ia3cf9413cd23af476bb5d2e6d70bee15234cbd11

ti: k3: drivers: sec_proxy: Fix printf format specifiers ...

The ID of a thread is not used outside for printing it out when
something goes wrong. The specifier used is also not consistent.
Instead of storing the thread ID, store its name and print that.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Id137c2f8dfdd5c599e220193344ece903f80af7b

Merge "Cortex A9: Fix typo in errata 794073 workaround" into integration

Merge "Neoverse N1: Forces cacheable atomic to near" into integration

Merge changes from topic "yg/optee" into integration ...

* changes:
  stm32mp1: add OP-TEE support
  stm32mp1: fix TZC400 configuration against non-secure DDR
  stm32mp1: remove useless define
  stm32mp: split stm32mp_io_setup function

stm32mp1: add OP-TEE support ...

Support booting OP-TEE as BL32 boot stage and secure runtime
service.

OP-TEE executes in internal RAM and uses a secure DDR area to store
the pager pagestore. Memory mapping and TZC are configured accordingly
prior OP-TEE boot. OP-TEE image is expected in OP-TEE v2 format where
a header file describes the effective boot images. This change
post processes header file content to get OP-TEE load addresses
and set OP-TEE boot arguments.

Change-Id: I02ef8b915e4be3e95b27029357d799d70e01cd44
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: fix TZC400 configuration against non-secure DDR ...

This change disables secure accesses to non-secure DDR which are useless.
TF-A already maps non-secure memory with non-secure permissions thanks
to the MMU.

This change also corrects some inline comments.

Change-Id: Id4c20c9ee5c95a666dae6b7446ed80baf2d53fb0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>