spm: Remove SPM Alpha 1 prototype and support files ...

The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component that, in turn, enables partition managers
at S-EL2 / S-EL1.

This patch removes:

- The core service files (std_svc/spm)
- The Resource Descriptor headers (include/services)
- SPRT protocol support and service definitions
- SPCI protocol support and service definitions

Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>

Remove dependency between SPM_MM and ENABLE_SPM build flags ...

There are two different implementations of Secure Partition
management in TF-A. One is based on the "Management Mode" (MM)
design, the other is based on the Secure Partition Client Interface
(SPCI) specification. Currently there is a dependency between their
build flags that shouldn't exist, making further development
harder than it should be. This patch removes that
dependency, making the two flags function independently.

Before: ENABLE_SPM=1 is required for using either implementation.
        By default, the SPCI-based implementation is enabled and
        this is overridden if SPM_MM=1.

After: ENABLE_SPM=1 enables the SPCI-based implementation.
       SPM_MM=1 enables the MM-based implementation.
       The two build flags are mutually exclusive.

Note that the name of the ENABLE_SPM flag remains a bit
ambiguous - this will be improved in a subsequent patch. For this
patch the intention was to leave the name as-is so that it is
easier to track the changes that were made.

Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Merge changes from topic "bs/pmf32" into integration ...

* changes:
  pmf: Make the runtime instrumentation work on AArch32
  SiP: Don't validate entrypoint if state switch is impossible

Merge changes from topic "tegra-boot-fixes-121719" into integration ...

* changes:
  Tegra: prepare boot parameters for Trusty
  Tegra: per-CPU GIC CPU interface init

Merge changes from topic "mailbox-fixes" into integration ...

* changes:
  intel: Fix SMC SIP service
  intel: Introduce mailbox response length handling
  intel: Fix mailbox config return status
  intel: Mailbox driver logic fixes
  plat: intel: Fix FPGA manager on reconfiguration
  plat: intel: Fix mailbox send_cmd issue
  intel: Modify mailbox's get_config_status

Merge "fdts: a5ds: cleanup enable-method in devicetree" into integration

Merge "TF-A: Fix BL2 bug in dynamic configuration initialisation" into integration

TF-A: Fix BL2 bug in dynamic configuration initialisation ...

This patch fixes the bug in BL2 dynamic configuration initialisation
which prevents loading NT_FW_CONFIG image (ref. GENFW-3471).
It also adds parentheses around 'if' statement conditions to fix
Coverity defect.

Change-Id: I353566c29b84341887e13bf8098a4fedfc4e00ff
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "fdts: a5ds: add L2 cache node in devicetree" into integration

Merge "intel: Create SiP service header file" into integration

fdts: a5ds: cleanup enable-method in devicetree ...

Same enable method is used by all the four cores. So,
make it globally for all the cores instead of adding
it to individual level.

Change-Id: I9b5728b0e0545c9e27160ea586009d929eb78cad
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

fdts: a5ds: add L2 cache node in devicetree ...

This change is to add L2 cache node into a5ds device tree.

Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

Merge "drivers: marvell: comphy-a3700: support SGMII COMPHY power off" into integration

Tegra: prepare boot parameters for Trusty ...

This patch saves the boot parameters provided by the previous bootloader
during cold boot and passes them to Trusty. Commit 06ff251ec introduced
the plat_trusty_set_boot_args() handler, but did not consider the boot
parameters passed by the previous bootloader. This patch fixes that
anomaly.

Change-Id: Ib40dcd02b67c94cea5cefce09edb0be4a998db37
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Merge "drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2" into integration

Merge changes from topic "nonbl2-boot" into integration ...

* changes:
  intel: stratix10: Modify BL31 parameter handling
  intel: Modify BL31 address mapping
  intel: stratix10: Enable uboot entrypoint support

Merge "aarch64: Fix stack pointer maintenance on EA handling path" into integration

aarch64: Fix stack pointer maintenance on EA handling path ...

EA handlers for exceptions taken from lower ELs at the end invokes
el3_exit function. However there was a bug with sp maintenance which
resulted in el3_exit setting runtime stack to context. This in turn
caused memory corruption on consecutive EL3 entries.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0424245c27c369c864506f4baa719968890ce659

Tegra: per-CPU GIC CPU interface init ...

This patch enables per-CPU GIC CPU interfaces during CPU
power on. The previous code initialized the distributor
for all CPUs, which was not required.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifd957b2367da06405b4c3e2225411adbaec35bb8

Merge changes from topic "allwinner_pmic" into integration ...

* changes:
  allwinner: h6: power: Switch to using the AXP driver
  drivers: allwinner: axp: Add AXP805 support

Merge "arm: gicv3: Fix compiler dependent behavior" into integration

Merge "plat/rockchip: enable power domains of rk3399 before reset" into integration

Merge "plat/rockchip: cliam a macro to enable hdcp feature for DP" into integration

pmf: Make the runtime instrumentation work on AArch32 ...

Ported the pmf asm macros and the asm code in the bl31 entrypoint
necessary for the instrumentation to AArch32.

Since smc dispatch is handled by the bl32 payload on AArch32, we
provide this service only if AARCH32_SP=sp_min is set.

Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac

SiP: Don't validate entrypoint if state switch is impossible ...

Switching execution states is only possible if EL3 is AArch64.
As such there is no need to validate the entrypoint on AArch32 builds.

Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: I3c1eb25b5df296a492870641d274bf65213c6608

intel: Fix SMC SIP service ...

Fix FPGA reconfiguration driver logic

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0299c1a71f3456e9b441340314662494b8d3e4a0

intel: Introduce mailbox response length handling ...

Mailbox driver now handles variable response length

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic96854fdaadaf48379c5de688392df974e1c99c3

intel: Fix mailbox config return status ...

Modify mailbox config return code to improve debugging.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0a223291f4c5296203b3295a679a5857a446c692

intel: Mailbox driver logic fixes ...

Fix mailbox driver urgent command handling, doorbell routine,
and logic optimization.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If536a383f449ca2a68d60274303ec24f92411505

plat: intel: Fix FPGA manager on reconfiguration ...

Fixes the SiP Service driver that is responsible for FPGA
reconfiguration. Also change the base address of FPGA reconfiguration
to 0x400000.

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8