| 2020-03-06 |
TSP: corrected log information
...
In CPU resume function, CPU suspend count was printed instead of CPU
resume count.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I0c081dc03a4ccfb2129687f690667c5ceed00a5f
Manish Pandey
committed
on 6 Mar 2020
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uniphier: shrink UNIPHIER_ROM_REGION_SIZE
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Currently, the ROM region is needlessly too large.
The on-chip SRAM region of the next SoC will start from 0x04000000,
and this will cause the region overlap.
Mapping 0x04000000 for the ROM is enough.
Change-Id: I85ce0bb1120ebff2e3bc7fd13dc0fd15dfff5ff6
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada
committed
on 6 Mar 2020
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Merge "driver/arm/css: minor bug fix" into integration
Alexei Fedorov
authored
on 6 Mar 2020
TrustedFirmware Code Review
committed
on 6 Mar 2020
|
qemu: Support optional encryption of BL31 and BL32 images
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Enable encryption IO layer to be stacked above FIP IO layer for optional
encryption of Bl31 and BL32 images in case ENCRYPT_BL31 or ENCRYPT_BL32
build flag is set.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I24cba64728861e833abffc3d5d9807599c49feb6
Sumit Garg
committed
on 6 Mar 2020
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qemu: Update flash address map to keep FIP in secure FLASH0
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Secure FLASH0 memory map looks like:
- Offset: 0 to 256K -> bl1.bin
- Offset: 256K to 4.25M -> fip.bin
FLASH1 is normally used via UEFI/edk2 to keep varstore.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I6883f556c22d6a5d3fa3846c703bebc2abe36765
Sumit Garg
committed
on 6 Mar 2020
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Makefile: Add support to optionally encrypt BL31 and BL32
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Following build flags have been added to support optional firmware
encryption:
- FW_ENC_STATUS: Top level firmware's encryption numeric flag, values:
0: Encryption is done with Secret Symmetric Key (SSK) which is
common for a class of devices.
1: Encryption is done with Binding Secret Symmetric Key (BSSK) which
is unique per device.
- ENC_KEY: A 32-byte (256-bit) symmetric key in hex string format. It
could be SSK or BSSK depending on FW_ENC_STATUS flag.
- ENC_NONCE: A 12-byte (96-bit) encryption nonce or Initialization Vector
(IV) in hex string format.
- ENCRYPT_BL31: Binary flag to enable encryption of BL31 firmware.
- ENCRYPT_BL32: Binary flag to enable encryption of Secure BL32 payload.
Similar flags can be added to encrypt other firmwares as well depending
on use-cases.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I94374d6830ad5908df557f63823e58383d8ad670
Sumit Garg
committed
on 6 Mar 2020
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tools: Add firmware authenticated encryption tool
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Add firmware authenticated encryption tool which utilizes OpenSSL
library to encrypt firmwares using a key provided via cmdline. Currently
this tool supports AES-GCM as an authenticated encryption algorithm.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I60e296af1b98f1912a19d5f91066be7ea85836e4
Sumit Garg
committed
on 6 Mar 2020
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TBB: Add an IO abstraction layer to load encrypted firmwares
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TBBR spec advocates for optional encryption of firmwares (see optional
requirement: R060_TBBR_FUNCTION). So add an IO abstaction layer to
support firmware decryption that can be stacked above any underlying IO/
packaging layer like FIP etc. It aims to provide a framework to load any
encrypted IO payload.
Also, add plat_get_enc_key_info() to be implemented in a platform
specific manner as handling of encryption key may vary from one platform
to another.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I9892e0ddf00ebecb8981301dbfa41ea23e078b03
Sumit Garg
committed
on 6 Mar 2020
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drivers: crypto: Add authenticated decryption framework
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Add framework for autheticated decryption of data. Currently this
patch optionally imports mbedtls library as a backend if build option
"DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated decryption
using AES-GCM algorithm.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I2966f0e79033151012bf4ffc66f484cd949e7271
Sumit Garg
committed
on 6 Mar 2020
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Merge changes from topic "spmd-sel2" into integration
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* changes:
SPMD: add command line parameter to run SPM at S-EL2 or S-EL1
SPMD: smc handler qualify secure origin using booleans
SPMD: SPMC init, SMC handler cosmetic changes
SPMD: [tegra] rename el1_sys_regs structure to sys_regs
SPMD: Adds partially supported EL2 registers.
SPMD: save/restore EL2 system registers.
Olivier Deprez
authored
on 6 Mar 2020
TrustedFirmware Code Review
committed
on 6 Mar 2020
|
| 2020-03-05 |
Merge changes from topic "console_t_drvdata_fix" into integration
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* changes:
imx: console: Use CONSOLE_T_BASE for UART base address
Tegra: spe: use CONSOLE_T_BASE to save MMIO base address
Manish Pandey
authored
on 5 Mar 2020
TrustedFirmware Code Review
committed
on 5 Mar 2020
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plat: imx8mm: provide uart base as build option
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Some boards (f.e. Verdin i.MX8M Mini) use different UART base address
for serial debug output, so make this value configurable (as a
build option).
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I988492ccecbc3f64a5153b381c4a97b8a0181f52
Igor Opaniuk
committed
on 5 Mar 2020
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driver/arm/css: minor bug fix
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The cpu index was wrongly checked causing it to assert always.
Since this code path is exercised only during TF test "NODE_HW_STAT",
which queries Power state from SCP, this bug was not detected earlier.
Change-Id: Ia25cef4c0aa23ed08092df39134937a2601c21ac
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Manish Pandey
committed
on 5 Mar 2020
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imx: console: Use CONSOLE_T_BASE for UART base address
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Since commit ac71344e9eca we have the UART base address in the generic
console_t structure. For most platforms the platform-specific struct
console is gone, so we *must* use the embedded base address, since there
is no storage behind the generic console_t anymore.
Replace the usage of CONSOLE_T_DRVDATA with CONSOLE_T_BASE to fix this.
Change-Id: I6d2ab0bc2c845c71f98b9dd64d89eef3252f4591
Reported-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara
committed
on 5 Mar 2020
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Tegra: spe: use CONSOLE_T_BASE to save MMIO base address
...
Commit ac71344 moved the base address
for the MMIO aperture of the console inside the console_t struct. As
a result, the driver should now save the MMIO base address to console_t
at offset marked by the CONSOLE_T_BASE macro.
This patch updates the SPE console driver to use the CONSOLE_T_BASE macro
to save/access the MMIO base address.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I42afc2608372687832932269108ed642f218fd40
Varun Wadekar
authored
on 4 Mar 2020
Andre Przywara
committed
on 5 Mar 2020
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Merge changes from topic "sp_loading" into integration
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* changes:
SPMD: loading Secure Partition payloads
fvp: add Cactus/Ivy Secure Partition information
fconf: Add Secure Partitions information as property
Olivier Deprez
authored
on 5 Mar 2020
TrustedFirmware Code Review
committed
on 5 Mar 2020
|
| 2020-03-04 |
fdts: a5ds: add ethernet node in devicetree
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This change is to add ethernet and voltage regulator nodes into
a5ds devicetree.
Change-Id: If9ed67040d54e76af1813c9f99835f51f617e9df
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Vishnu Banavath
committed
on 4 Mar 2020
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SPMD: loading Secure Partition payloads
...
This patch implements loading of Secure Partition packages using
existing framework of loading other bl images.
The current framework uses a statically defined array to store all the
possible image types and at run time generates a link list and traverse
through it to load different images.
To load SPs, a new array of fixed size is introduced which will be
dynamically populated based on number of SPs available in the system
and it will be appended to the loadable images list.
Change-Id: I8309f63595f2a71b28a73b922d20ccba9c4f6ae4
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Manish Pandey
committed
on 4 Mar 2020
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| 2020-03-03 |
Merge "Update pathnames in maintainers.rst file" into integration
Sandrine Bailleux
authored
on 3 Mar 2020
TrustedFirmware Code Review
committed
on 3 Mar 2020
|
SPMD: add command line parameter to run SPM at S-EL2 or S-EL1
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Added SPMD_SPM_AT_SEL2 build command line parameter.
Set to 1 to run SPM at S-EL2.
Set to 0 to run SPM at S-EL1 (pre-v8.4 or S-EL2 is disabled).
Removed runtime EL from SPM core manifest.
Change-Id: Icb4f5ea4c800f266880db1d410d63fe27a1171c0
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Max Shvetsov
committed
on 3 Mar 2020
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SPMD: smc handler qualify secure origin using booleans
...
Change-Id: Icc8f73660453a2cbb2241583684b615d5d1af9d4
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Olivier Deprez
authored
on 23 Dec 2019
Max Shvetsov
committed
on 3 Mar 2020
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SPMD: SPMC init, SMC handler cosmetic changes
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Change-Id: I8881d489994aea667e3dd59932ab4123f511d6ba
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Max Shvetsov
committed
on 3 Mar 2020
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SPMD: [tegra] rename el1_sys_regs structure to sys_regs
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Renamed the structure according to a SPMD refactoring
introduced in <c585d07aa> since this structure is used
to service both EL1 and EL2 as opposed to serving only EL1.
Change-Id: I23b7c089e53f617157a4b4e6443acce50d85c3b5
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Max Shvetsov
committed
on 3 Mar 2020
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SPMD: Adds partially supported EL2 registers.
...
This patch adds EL2 registers that are supported up to ARMv8.6.
ARM_ARCH_MINOR has to specified to enable save/restore routine.
Note: Following registers are still not covered in save/restore.
* AMEVCNTVOFF0<n>_EL2
* AMEVCNTVOFF1<n>_EL2
* ICH_AP0R<n>_EL2
* ICH_AP1R<n>_EL2
* ICH_LR<n>_EL2
Change-Id: I4813f3243e56e21cb297b31ef549a4b38d4876e1
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Max Shvetsov
committed
on 3 Mar 2020
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fvp: add Cactus/Ivy Secure Partition information
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Add load address and UUID in fw config dts for Cactus and Ivy which are
example SP's in tf-test repository.
For prototype purpose these information is added manually but later on
it will be updated at compile time from SP layout file and SP manifests
provided by platform.
Change-Id: I41f485e0245d882c7b514bad41fae34036597ce4
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Manish Pandey
committed
on 3 Mar 2020
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fconf: Add Secure Partitions information as property
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Use the firmware configuration framework to retrieve information about
Secure Partitions to facilitate loading them into memory.
To load a SP image we need UUID look-up into FIP and the load address
where it needs to be loaded in memory.
This patch introduces a SP populator function which gets UUID and load
address from firmware config device tree and updates its C data
structure.
Change-Id: I17faec41803df9a76712dcc8b67cadb1c9daf8cd
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Olivier Deprez
authored
on 23 Jan 2020
Manish Pandey
committed
on 3 Mar 2020
|
| 2020-03-02 |
hikey960: Enable system power off callback
...
On Hikey960 if outputs GPIO176 low level, it can tell PMIC to power off
the whole board. To avoid resetting the board and stay off, it also
requires the SW2201's three switches 1/2/3 need to be all set to 0.
Since current code doesn't contain complete GPIO modules and misses to
support GPIO176. This patch adds all known GPIO modules and initialize
GPIO in BL31, and adds system power off callback to use GPIO176 for PMIC
power off operation.
Change-Id: Ia88859b8b7c87c061420ef75f0de3e2768667bb0
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Leo Yan
committed
on 2 Mar 2020
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Merge "doc: Fix variables names in TBBR CoT documentation" into integration
Sandrine Bailleux
authored
on 2 Mar 2020
TrustedFirmware Code Review
committed
on 2 Mar 2020
|
doc: Fix variables names in TBBR CoT documentation
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In commit 516beb5 ("TBB: apply TBBR naming
convention to certificates and extensions"), some of the variables used in the
TBBR chain of trust got renamed but the documentation did not get properly
updated everywhere to reflect these changes.
Change-Id: Ie8e2146882c2d3538c5b8c968d1bdaf5ea2a6e53
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux
committed
on 2 Mar 2020
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SPMD: save/restore EL2 system registers.
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NOTE: Not all EL-2 system registers are saved/restored.
This subset includes registers recognized by ARMv8.0
Change-Id: I9993c7d78d8f5f8e72d1c6c8d6fd871283aa3ce0
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Max Shvetsov
committed
on 2 Mar 2020
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